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Browse Prior Art Database

High Performance Integrated Array Cell

IP.com Disclosure Number: IPCOM000047598D
Original Publication Date: 1983-Dec-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 34K

Publishing Venue

IBM

Related People

Barish, AE: AUTHOR [+2]

Abstract

The disclosed array cell is a fast, DC stable cell, which can be integrated on an ECL logic masterslice. It offers high DC stability by providing a compensated reference (centered around the two-array stable-state levels). The array cell devices are integrated into the silicon, under the first metal wiring channels, and the contacts are personalized when the cell is used. Operation of the cell is as follows: A. Write Operation The word line of the selected cell (base inputs of transistors T3 and T4) is raised to a logical "1" state. In the write mode, the left or right bit line is lowered by the bit line driver (which acts as a constant current source) which turns on T3 or T4, respectively. This causes node C1 or C2, respectively, to change to a logical "0" state and allow the cell to change state. B.

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High Performance Integrated Array Cell

The disclosed array cell is a fast, DC stable cell, which can be integrated on an ECL logic masterslice. It offers high DC stability by providing a compensated reference (centered around the two-array stable-state levels). The array cell devices are integrated into the silicon, under the first metal wiring channels, and the contacts are personalized when the cell is used. Operation of the cell is as follows: A. Write Operation The word line of the selected cell (base inputs of transistors T3 and T4) is raised to a logical "1" state. In the write mode, the left or right bit line is lowered by the bit line driver (which acts as a constant current source) which turns on T3 or T4, respectively. This causes node C1 or C2, respectively, to change to a logical "0" state and allow the cell to change state. B. Read Operation Both the left and right bit lines are in the logical "1" state. This assures that the cell will not be disturbed because the word line is also at this logical state.

The word line is used to activate the read circuit (not shown, one per array cell). When reading, only base current is drawn from either the read reference voltage or the read circuit input, hence, providing no read disturb. Read and Write circuits, which may be employed with the subject cell, are disclosed in the following article.

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