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Dynamic Memory Output Reorganization

IP.com Disclosure Number: IPCOM000047600D
Original Publication Date: 1983-Dec-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 3 page(s) / 33K

Publishing Venue

IBM

Related People

Kimmel, RD: AUTHOR [+2]

Abstract

Described here is a technique for designing memory arrays that have a user-selectable output word organization. This is accomplished by imbedding multiplexer circuitry into the array access mechanism, controlled by external logic signals. The advantage in this approach is that it allows the capability of multiple external organizations from a single part, making the part more versatile in a number of ways: design and manufacturing costs are reduced, as well as inventory costs. In addition, when the multiplexer select time is comparable to the overall array cycle time, dynamic reconfiguration is possible, allowing the chip to have different external appearances in the same application. This can lead to new applications that were not previously possible due to inter-chip delay times.

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Dynamic Memory Output Reorganization

Described here is a technique for designing memory arrays that have a user- selectable output word organization. This is accomplished by imbedding multiplexer circuitry into the array access mechanism, controlled by external logic signals. The advantage in this approach is that it allows the capability of multiple external organizations from a single part, making the part more versatile in a number of ways: design and manufacturing costs are reduced, as well as inventory costs. In addition, when the multiplexer select time is comparable to the overall array cycle time, dynamic reconfiguration is possible, allowing the chip to have different external appearances in the same application. This can lead to new applications that were not previously possible due to inter-chip delay times. In memory array design and applications, "organization" refers to the mapping of an N-bit array into an external representation of p words, each consisting of q=N/p bits. Such mapping is often referred to as "p x q". The internal organization of a memory array often differs from its external organization, allowing the internal organization of the array to best conform to the electrical design requirements. Conventional design techniques fix the external organization during the manufacturing process. The unique feature suggested here is the use of an additional logic function in the array access mechanism to allow the external organization to be altered dynamically. The elements of this approach are quite simple. A wide word is addressed from the memory array, and the contents of this word are either placed directly onto the output lines or multiplexed onto a subset of the output lines. The actual output function is controlled logically by control lines which are enabled for the desired mode. The control lines consist of a set of mode select lines and/or a set of multiplexer select lines. The drawing shows a simple example of this concept, using a single mode select line to select between two different organizations (which also performs the multiplexer select function). The memory array is directly addressed to yield an 8-bit word, which is then processed by the new multiplexer circuitry. In this example, the origin...