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Clock Driver Circuit

IP.com Disclosure Number: IPCOM000047603D
Original Publication Date: 1983-Dec-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 37K

Publishing Venue

IBM

Related People

Culican, EF: AUTHOR [+2]

Abstract

Testing is a concern in the VLSI environment. One way to address testing consideration is the extension of Level Sensitive Scan Design (LSSD) [1] to the chip boundary (ECIPT), as disclosed in [2]. In order to supply the proper clock inputs to the shift register latch (not shown) the driver circuit shown in the drawing may be employed. To generate the appropriate Up level >1.7 V an emitter follower with an Up-level clamp is employed. This gives a typical output of approximately 2.1 V at 5 ma. It should be noted that the design is for DC current in the Up level instead of DC current in the Down level. The input circuitry produces the AOI logical function; a "1" on IN3 or IN1 and IN2 will force the output Down.

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Clock Driver Circuit

Testing is a concern in the VLSI environment. One way to address testing consideration is the extension of Level Sensitive Scan Design (LSSD) [1] to the chip boundary (ECIPT), as disclosed in [2]. In order to supply the proper clock inputs to the shift register latch (not shown) the driver circuit shown in the drawing may be employed. To generate the appropriate Up level >1.7 V an emitter follower with an Up-level clamp is employed. This gives a typical output of approximately 2.1 V at 5 ma. It should be noted that the design is for DC current in the Up level instead of DC current in the Down level. The input circuitry produces the AOI logical function; a "1" on IN3 or IN1 and IN2 will force the output Down. IN1 and IN2 are used to produce distinct thresholds, with the IN1 threshold higher than that of the latch and the IN2 threshold lower than that of the latch. This allows dual clock generator designs to produce proper latch operation. References 1. E. B. Eichelberger and T. W. Williams, "A Logic Design Structure for LSI Testability," 14th Design Automation Conference Proceedings, June 20, 21 and 22, 1977, New Orleans, Louisiana. IEEE Catalog Number CH1216-1C, pages 462-468. 2. M. T. McMahon and P. Goel, "Electronic Chip In Place Test (ECIPT)," ACM IEEE Design Automation Conference, Caesar's Palace, Las Vegas, Nevada (Session 30, entitled "Enhancement to Scan Design Techniques, June 15, 1982) June 14-16, 1982.

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