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B Clock Driver for Electronic Chip in Place Test

IP.com Disclosure Number: IPCOM000047604D
Original Publication Date: 1983-Dec-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 50K

Publishing Venue

IBM

Related People

Culican, EF: AUTHOR [+2]

Abstract

In extending Level Sensitive Scan design (LSSD) [1] to the chip boundaries (electronic chip in place test (ECIPT)), as described in [2], a custom 12 latch may be employed. The custom latch minimizes the overhead area on the chip. Since the 12 latch requires special drives, the B clock driver may be utilized. The block diagram for the B clock driver for ECIPT is illustrated in Fig. 1. Fig. 2 shows the driver circuit, and Fig. 3 shows the ECIPT 12 latch. Examining the latch, its threshold can be seen to be approximately 1.35 V. For proper latch function, the B signal must reach the latch threshold before the B input is allowed to change. Examining the circuit of the driver, its threshold is approximately 1.4 V. For the critical latch operation (B rising), the latch will set when B reaches 1.35 V but stage 4 (Fig.

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B Clock Driver for Electronic Chip in Place Test

In extending Level Sensitive Scan design (LSSD) [1] to the chip boundaries (electronic chip in place test (ECIPT)), as described in [2], a custom 12 latch may be employed. The custom latch minimizes the overhead area on the chip. Since the 12 latch requires special drives, the B clock driver may be utilized. The block diagram for the B clock driver for ECIPT is illustrated in Fig. 1. Fig. 2 shows the driver circuit, and Fig. 3 shows the ECIPT 12 latch. Examining the latch, its threshold can be seen to be approximately 1.35 V. For proper latch function, the B signal must reach the latch threshold before the B input is allowed to change. Examining the circuit of the driver, its threshold is approximately 1.4 V. For the critical latch operation (B rising), the latch will set when B reaches 1.35 V but stage 4 (Fig. 1) will not start to change until 1.4 V, guaranteeing proper latch function. References 1. E. B. Eichelberger and T. W. Williams, "A Logic Design Structure For LSI Testability," 14th Design Automation Conference Proceedings, June 20, 21 and 22, 1977, New Orleans, Louisiana. IEEE Catalog Number CH1216-1C, pages 462-468. 2. M. T. Mc Mahon and P. Goel, "Electronic Chip In Place Test (ECIPT)," ACM IEEE Design Automation Conference, Caesar's Palace, Las Vegas, Nevada (Session 30, entitled "Enhancement to Scan Design Techniques, June 15, 1982) June 14-16, 1982.

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