Browse Prior Art Database

Method of Monitoring a Semiconductor Line for Shock Imparted to Product

IP.com Disclosure Number: IPCOM000047607D
Original Publication Date: 1983-Dec-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 25K

Publishing Venue

IBM

Related People

Fouts, DP: AUTHOR [+4]

Abstract

Semiconductor chips on a multi-chip module may be employed as load transducers to monitor a semiconductor assembly line for shock imparted to modules assembled on the line. It is known that any bending imparted to a semiconductor chip during assembly will create stresses that will alter the device performance/characteristics. Figs. 1 and 2 are distribution plots of switching performance versus output voltage of a semiconductor chip before and after mechanical impact. Fig. 2 shows that the switching performance of a chip has been significantly reduced when the chip is subjected to mechanical impact during manufacturing on the semiconductor line.

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Method of Monitoring a Semiconductor Line for Shock Imparted to Product

Semiconductor chips on a multi-chip module may be employed as load transducers to monitor a semiconductor assembly line for shock imparted to modules assembled on the line. It is known that any bending imparted to a semiconductor chip during assembly will create stresses that will alter the device performance/characteristics. Figs. 1 and 2 are distribution plots of switching performance versus output voltage of a semiconductor chip before and after mechanical impact. Fig. 2 shows that the switching performance of a chip has been significantly reduced when the chip is subjected to mechanical impact during manufacturing on the semiconductor line. Applying this principle, an assembly line can be monitored to determine the effect of the various processes on a chip from a shock standpoint by testing a passenger or dummy chip on a module at the end of all process operations. The shift in chip performance due to mechanical impact can be compared to the performance of pre-calibrated chips that are normally expected as a part of a module that proceeds through the line. The difference in actual versus expected performance can be used as a benchmark to initiate corrective action, when necessary, to minimize the effect of impact to the product.

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