Browse Prior Art Database

Late Address Path

IP.com Disclosure Number: IPCOM000047687D
Original Publication Date: 1983-Dec-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 3 page(s) / 67K

Publishing Venue

IBM

Related People

Klein, W: AUTHOR [+4]

Abstract

In large storages with relatively slow storage cells, such as one-device cells, the access time is reduced by fast buffers being integrated on the storage chip. Assuming that the bytes consist of n bits, then these buffers are divided into n groups of 2N bits each, each group being directly connected to one of the n output drivers. In the case of an x$n organization, these buffers permit data blocks of 2N$n cells to be read at the same time and their information to be stored. As the connection between buffer and output driver is subject to a very short delay, it may be sufficient for part of the addresses, say, 2, in the case of 4$n buffers, and 3, in the case of 8$n buffers, to be switched only shortly before the time at which the output data are specified to be valid.

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Late Address Path

In large storages with relatively slow storage cells, such as one-device cells, the access time is reduced by fast buffers being integrated on the storage chip. Assuming that the bytes consist of n bits, then these buffers are divided into n groups of 2N bits each, each group being directly connected to one of the n output drivers.

In the case of an x$n organization, these buffers permit data blocks of 2N$n cells to be read at the same time and their information to be stored. As the connection between buffer and output driver is subject to a very short delay, it may be sufficient for part of the addresses, say, 2, in the case of 4$n buffers, and 3, in the case of 8$n buffers, to be switched only shortly before the time at which the output data are specified to be valid. The requirement of having a short access time is met by using buffers for part of the data which are controlled by so-called late addresses. In such a case, it is irrelevant for the user that a large data block has been written into the buffers integrated on the chip. What is important, however, is that there is a minimum time period between setting the addresses and the time at which the output signal is valid. Therefore, a novel circuit concept is proposed which meets this requirement at extremely short access times. The circuit diagram of Fig. 1 permits the late addresses to select part (n out of m) of the buffers and to simultaneously control the data-out enable/disable function. During a read operation, a data block of m bytes is loaded into m$n buffers through preamplifiers SA and read amplifiers RA. In four cycles closely following each other, the information of the buffers can be passed on to n output drivers by means of the late addresses AL0 and AL1. For this purpose, the two late addresses are decoded in the late address decoder, whose four outputs D0G0 ... D0G3 control the four circuits D0G. For selection, only one of these four outputs is pulled to its down level. By means of a current switch for short switching times, each circuit D0G generates two complementary output signals LIL and D0GX. As soon as one of the outputs D0G0 ... D0G3 is set to the selected down level, the appertaining LIL line...