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Pulse Base Circuit for Shorter Restore Operation in MTL Arrays

IP.com Disclosure Number: IPCOM000047688D
Original Publication Date: 1983-Dec-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 3 page(s) / 63K

Publishing Venue

IBM

Related People

Klein, W: AUTHOR [+3]

Abstract

A large part of the cycle time of merged transistor logic (MTL) storages is needed for the restore phase at the end of each read/write operation. To achieve shorter cycle times, it is necessary, therefore, to reduce the restore time to a minimum. During a read/write operation, the bit line transistors TBL, belonging to the selected bit line pair, are switched off. This is done by means of the bit switch transistor TBS, series-connected to transistor T3, whose switching state is controlled by the bit decoder and an internal control signal CLOCK 2. The output potential of a selected bit decoder is at an up level, so that the appertaining transistor TBS is switched on as soon as the potential of the CLOCK 2 line is switched to ground GND. As a result, the collector potential of transistor TBS drops to 0.

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Pulse Base Circuit for Shorter Restore Operation in MTL Arrays

A large part of the cycle time of merged transistor logic (MTL) storages is needed for the restore phase at the end of each read/write operation. To achieve shorter cycle times, it is necessary, therefore, to reduce the restore time to a minimum. During a read/write operation, the bit line transistors TBL, belonging to the selected bit line pair, are switched off. This is done by means of the bit switch transistor TBS, series-connected to transistor T3, whose switching state is controlled by the bit decoder and an internal control signal CLOCK 2. The output potential of a selected bit decoder is at an up level, so that the appertaining transistor TBS is switched on as soon as the potential of the CLOCK 2 line is switched to ground GND. As a result, the collector potential of transistor TBS drops to 0.1 V, and the relevant bit line transistors TBL are switched off by the Schottky diode SB. It is only at this stage that the voltage of the bit restore line BRL is reduced by 400 mV, in order to decrease the potential of the unselected bit lines BL through the (unselected) bit line transistors TBL which are still switched on. This is necessary to permit the word line transistors TWL to pull down the selected word line WL more rapidly. The different switching states of the selected and the unselected bit line transistors TBL lead to a potential difference of about 1.2 V to be applied to the base nodes BB at the end of the read/write operation before the restore function is implemented. This means that after the array restore circuit has again raised the potential of line BRL to its standby level, the restore current flows initially only through bit line transistors TBL of the unselected bit lines BL.

It is only after the base current, supplied by the decoupling resistors RB, has raised the base potential of the selected bit line transistors TBL to a value as high as that of the base potential of the unselected b...