Browse Prior Art Database

SERIAL BUS Ring Protocol for Single-Chip Micro-Computers

IP.com Disclosure Number: IPCOM000047705D
Original Publication Date: 1983-Dec-01
Included in the Prior Art Database: 2005-Feb-08
Document File: 5 page(s) / 42K

Publishing Venue

IBM

Related People

Holcomb, DW: AUTHOR [+2]

Abstract

Disclosed is a means by which several micro-computers having the serial interface capability of the Intel 8051 micro-processor may communicate over a single wire serial bus in a ring configuration. It is unique in its use of the ninth data bit to delineate both the start and end of a command sequence, the manner in which permission to transmit (Token Control) is achieved, and the use of the Data Pacing Line to prevent loss of data (overrun) during a multi-byte data transmission. Background In the design of, for example, low cost electronic typewriters, it is often desirable to use single-chip micro-computers, such as the Intel 8051, to perform device control and text processing control functions.

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SERIAL BUS Ring Protocol for Single-Chip Micro-Computers

Disclosed is a means by which several micro-computers having the serial interface capability of the Intel 8051 micro-processor may communicate over a single wire serial bus in a ring configuration.

It is unique in its use of the ninth data bit to delineate both the start and end of a command sequence, the manner in which permission to transmit (Token Control) is achieved, and the use of the Data Pacing Line to prevent loss of data (overrun) during a multi-byte data transmission. Background In the design of, for example, low cost electronic typewriters, it is often desirable to use single-chip micro-computers, such as the Intel 8051, to perform device control and text processing control functions. By using several processors, complex functions may be implemented and functional enhancements may more easily be made to already announced products. The serial interface is an efficient way to establish a communications path among such processing units. Described below is an efficient way to implement such a communications path. This article discusses the problems of addressing, bus arbitration (token control), control codes, and bus protocol. Interconnection of Processors The figure shows the connections of a plurality of 8051 processors. The protocol described below permits the connection of 15 such devices (limited only by the 4-bit address field). The line labeled "SERIAL BUS" is the bus used for communications in a full-duplex mode. Token Control Only one processor may initiate a command sequence at a time.

This is insured by allowing a processor to initiate a command only when it has control of the "Token". The Token is a unique one-byte command which is transmitted onto the bus following each command sequence. When a processor receives the Token, it may initiate a command (if required) or transmit the Token onto the next processor; this method of Token control is referred to as "Token Circulation" since the Token circulates around the ring of processors when no command sequence is in progress. Data Placing The 8051 serial interface provides the automatic buffering of two received bytes as long as the first byte is read from the Serial Bus before the last bit of the second byte is received. If the first byte is not read by the time the second byte is received, then the second byte is lost.

Since many device control applications dictate that a processor be completely utilized for periods of time which are longer than the time required to receive two bytes on the bus (less than 120 microseconds), a method of preventing data loss is required. This is achieved by the use of a Data Pacing hardware line in the following manner (see figure): Assume that processor X initiates a multiple byte command sequence to processor Z. At power-on time, each processor checks the state of the Data Pacing Line that connects it to the next processor on the Serial Bus. Each processor assumes that the...