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Digital Lock Detector for Phase-Locked Loop Circuit

IP.com Disclosure Number: IPCOM000047745D
Original Publication Date: 1983-Dec-01
Included in the Prior Art Database: 2005-Feb-08
Document File: 2 page(s) / 56K

Publishing Venue

IBM

Related People

Keller, H: AUTHOR [+2]

Abstract

A phase-locked loop (PLL) circuit for a communication system is provided with a digital lock detector. Details of such a lock detector are described in the following. One main application is in ring transmission systems operating with signals which are a Manchester code representation of the transmitted data. A block diagram of the digital lock detector is shown in Fig. 1, and respective waveforms are shown in Fig. 2. An associated phase diagram is depicted in Fig. 3. In the Manchester code, each data bit is represented by a pair of halfbits, e.g., a plus-minus pulse pair for a "1", and a minus-plus pulse pair for a "0".

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Digital Lock Detector for Phase-Locked Loop Circuit

A phase-locked loop (PLL) circuit for a communication system is provided with a digital lock detector. Details of such a lock detector are described in the following. One main application is in ring transmission systems operating with signals which are a Manchester code representation of the transmitted data. A block diagram of the digital lock detector is shown in Fig. 1, and respective waveforms are shown in Fig. 2. An associated phase diagram is depicted in Fig.
3. In the Manchester code, each data bit is represented by a pair of halfbits, e.g., a plus-minus pulse pair for a "1", and a minus-plus pulse pair for a "0". It is assumed that the basic data frequency is 4 Mbit/s, so that the frequency of the Manchester code halfbits is 8 Mbit/s, and that a voltage-controlled oscillator (VCO) of the PLL circuit furnishes rectangular pulse signals of 8 MHz and 16 MHz frequency (Fig. 2). From these basic pulse signals, four-phase quadrant signals A, B, C, and D are derived which represent the first, second, third, and fourth quadrants, respectively, as shown in Fig. 3. A data signal transition is considered to be in-phase if it falls into quadrants 1 and 4, i.e., if it coincides with phase quadrant signals A + D. A data signal transition is considered to be out- phase if it falls into quadrants 2 and 3, i.e., if it coincides with phase quadrant signals B and C. Design and operation of the lock detector is now explained in connection with Fig. 1. Quadrant encoder 10 receives basic 16 MHz and 8 MHz pulse signals and furnishes the two combined quadrant signals A D and B + C, respectively. These combined signals and the rec...