Browse Prior Art Database

Multiprocessor Control of Cached Peripheral Systems

IP.com Disclosure Number: IPCOM000047749D
Original Publication Date: 1983-Dec-01
Included in the Prior Art Database: 2005-Feb-08
Document File: 2 page(s) / 51K

Publishing Venue

IBM

Related People

Hoskinson, WC: AUTHOR [+2]

Abstract

A cached peripheral system, such as a tape or disk file peripheral storage system, has data transfers between an attached host processor and the cache simultaneous with the data transfers between the cache and peripheral data storage devices. Because of the rate of data transfers to and from the peripheral data storage devices, a single controlling processor is unable to appropriately supervise all the asynchronous data transfers. Accordingly, a secondary or slave "gap" processor closely supervises and controls the data transfers between the cache and the devices for relieving the other or main processor for operating the storage subsystem and performing other supervisory functions.

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Multiprocessor Control of Cached Peripheral Systems

A cached peripheral system, such as a tape or disk file peripheral storage system, has data transfers between an attached host processor and the cache simultaneous with the data transfers between the cache and peripheral data storage devices. Because of the rate of data transfers to and from the peripheral data storage devices, a single controlling processor is unable to appropriately supervise all the asynchronous data transfers. Accordingly, a secondary or slave "gap" processor closely supervises and controls the data transfers between the cache and the devices for relieving the other or main processor for operating the storage subsystem and performing other supervisory functions. The gap processor is clock synchronous with the main processor such that when the main processor clock rate changes between critical and non-critical programs, the gap processor clock rate likewise changes. This allows close coordination between the main and gap processors in the storage system. The figure shows a plurality of host processors coupled to the data storage system via a plurality of channel adapters. The peripheral data storage devices are coupled to the intervening cache through a modem adapter, cached-DASD data flow, while the cache is coupled to the channel adapters by a host-cache data flow. Additionally, the host processors can directly access the DASD via a host-DASD data flow. The latter connection is the same connection found in non-cached peripheral data storage systems. For speed matching the channel data transfers with the DASD data transfers, a FIFO (first-in, first-out) buffer is operatively associated with the host- DASD data flow. The main processor has a main control store storing its programs of instruction for operating the peripheral system and includes many connections (not shown) to the various elements of the data storage subsystem for controlling same. The gap processor communicates with the...