Browse Prior Art Database

Distributing Microcode Patches

IP.com Disclosure Number: IPCOM000047750D
Original Publication Date: 1983-Dec-01
Included in the Prior Art Database: 2005-Feb-08
Document File: 2 page(s) / 42K

Publishing Venue

IBM

Related People

Jeppson, OB: AUTHOR [+4]

Abstract

A peripheral data processing system having a plurality of peripheral devices, such as magnetic tape drives, have a read-only memory (ROM) for sequencing the microprocessor in the peripheral unit. Because of inherent delays in updating a ROM, each peripheral unit has a random-access memory (RAM) which stores patches to the code of the ROM. The RAM is called a patch memory (PM) and is sensed during the execution of the ROM programs by the microprocessor for substituting RAM-stored code patches for the ROM-stored code. Each PM in the peripheral units is updated each time the peripheral system is initially microprogram loaded (IML). A control unit of the peripheral subsystem senses the engineering change (EC) level of all the peripheral units and stores the EC number within the control unit.

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Distributing Microcode Patches

A peripheral data processing system having a plurality of peripheral devices, such as magnetic tape drives, have a read-only memory (ROM) for sequencing the microprocessor in the peripheral unit. Because of inherent delays in updating a ROM, each peripheral unit has a random-access memory (RAM) which stores patches to the code of the ROM. The RAM is called a patch memory (PM) and is sensed during the execution of the ROM programs by the microprocessor for substituting RAM-stored code patches for the ROM-stored code. Each PM in the peripheral units is updated each time the peripheral system is initially microprogram loaded (IML). A control unit of the peripheral subsystem senses the engineering change (EC) level of all the peripheral units and stores the EC number within the control unit. Then the control accesses a patch record which includes EC numbers for all of the code in the peripheral devices. The control unit reads the patches in accordance with EC level and directs the patches to the peripheral unit in accordance with the EC level. Emergency patches are relatable to EC levels and are handled accordingly; that is, an EC patch may have an emergency patch for a particular type of peripheral unit. Accessing the patch codes can be from a peripheral unit being patched, from a maintenance circuit, communications circuit from a remote site or a disk file, such as a flexible disk. A peripheral system attached to a host processor by a control unit is activated by the host processor through a set of manual switches (not shown) causing the control unit to IML. IML may be self-contained in the control unit or be through a maintenance device or circuit. As soon as the control unit has successfully IMLed, it senses the attached tape drives. When the tape drives have been activated, and passed through initial diagnostics, the control unit sends SENSE commands for reading the EC levels of all of the tape drives. Various ...