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Horizontal Scan Phase-Locked Loop Detector for Crt

IP.com Disclosure Number: IPCOM000047755D
Original Publication Date: 1983-Dec-01
Included in the Prior Art Database: 2005-Feb-08
Document File: 3 page(s) / 46K

Publishing Venue

IBM

Related People

Anwyl, ED: AUTHOR [+2]

Abstract

A design for a phase comparator/detector has been proposed which by utilizing both the leading and trailing edges of the flyback and sync pulses in a horizontal scan circuit enabled phase lock to be achieved which was independent of either pulse width, was more accurately and consistently centered and enabled a more efficient horizontal scan design due to the improved phase locking. However, a shortcoming of this design involved the transfer function of the detector when out of phase lock. This can best be illustrated by means of Fig. 1. This shows the net early and/or late pulse width per cycle against phase offset. It can be seen that when approaching lock, the gain of the detector is 2, and when in lock the gain rises to 3, depending on the relative pulse widths and delayed sync overlap timings.

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Horizontal Scan Phase-Locked Loop Detector for Crt

A design for a phase comparator/detector has been proposed which by utilizing both the leading and trailing edges of the flyback and sync pulses in a horizontal scan circuit enabled phase lock to be achieved which was independent of either pulse width, was more accurately and consistently centered and enabled a more efficient horizontal scan design due to the improved phase locking. However, a shortcoming of this design involved the transfer function of the detector when out of phase lock. This can best be illustrated by means of Fig. 1. This shows the net early and/or late pulse width per cycle against phase offset. It can be seen that when approaching lock, the gain of the detector is 2, and when in lock the gain rises to 3, depending on the relative pulse widths and delayed sync overlap timings. Once the phase offset is greater than half the width of the smallest pulse (the flyback or sync), then the net early/late output pulse fails to increase any further and remains fixed in magnitude. This leads to a reduced phase detector gain when out of phase lock by more than tw/2, leading to a reduced capture range. As a result, the design becomes more sensitive to any offsets in the loop design such as can be introduced for phase shift controls (by means of an offsetting +VE or -VE current injected into the integrating capacitor) or those present due to circuit design limitations, and again the capture range is reduced and/or offset asymmetrically about the center frequency. This article describes a circuit which has the transfer characteristic shown in Fig. 2. It utilizes the leading and trailing edges of both the flyback reference pulse and the sync input, thus maintaining the advantages of the previous design. Also when approaching phase lock the gain of the detector remains at 2, thus maintaining the same system performance as the previous design; however, when out of lock, the gain only falls to a minimum of 1, which increases the capture range significantly and reduces the sensitivity of the capture range to loop offsets. With a more linear design of the phase detector, a second order phase-locked loop can approach the theoretical limits of capture and generally will be limited by the range of the voltage-controlled oscillator (VCO) which needs to be large enough to compensate for input frequency tolerances and/or its own tolerances. The improved capture range has removed the ne...