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Interstitial Vias for Improved Wirability

IP.com Disclosure Number: IPCOM000047773D
Original Publication Date: 1983-Dec-01
Included in the Prior Art Database: 2005-Feb-08
Document File: 1 page(s) / 11K

Publishing Venue

IBM

Related People

Girvan, EJ: AUTHOR [+4]

Abstract

The article describes an improved wiring scheme for printed circuit cards and boards which provide mid-channel escape. For 3 lines per channel printed circuit wiring random interstitial vias are used to enhance the escape of the center line. This maximizes the wiring capability of 3-line-per-channel printed circuits. It also provides a further increase in wiring density to 4 lines per channel. Access to the mid-channel lines is key to this extension. This improvement allows the use of 2-wiring-plane printed circuit boards in lieu of 3 and 4 wiring planes, the net result being increased productivity through design. This wiring scheme utilizes an interstitial via which is placed at random that is, where required, in the center of the standard grid matrix. Clearances between holes are thus maximized.

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Interstitial Vias for Improved Wirability

The article describes an improved wiring scheme for printed circuit cards and boards which provide mid-channel escape. For 3 lines per channel printed circuit wiring random interstitial vias are used to enhance the escape of the center line. This maximizes the wiring capability of 3-line-per-channel printed circuits. It also provides a further increase in wiring density to 4 lines per channel. Access to the mid-channel lines is key to this extension. This improvement allows the use of 2- wiring-plane printed circuit boards in lieu of 3 and 4 wiring planes, the net result being increased productivity through design. This wiring scheme utilizes an interstitial via which is placed at random that is, where required, in the center of the standard grid matrix. Clearances between holes are thus maximized. The via lands, both standard grid and interstitial, are octagonal or round rather than square to provide additional area for wiring. To compensate for any adverse affect of reduced copper in the internal power planes due to the addition of interstitial via holes, random standard grid vias may be used. This further enhances the wirability of 2-wiring-plane products with additional lines per channel. This technique is not limited to the low end packaging technology of a 2- wiring-plane design. It applies to the high end as well, where 4 or more wiring planes are required.

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