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In-Stream Logic Simulation Non-Orthogonality Verification for Current-Mode Logic Technology Collector Dotting

IP.com Disclosure Number: IPCOM000047792D
Original Publication Date: 1983-Dec-01
Included in the Prior Art Database: 2005-Feb-08
Document File: 3 page(s) / 49K

IBM

Related People

Davis, JW: AUTHOR [+2]

Abstract

Non-orthogonality between collector dots of current-mode logic technology is checked and verified by means of conventional logic and error induction. The method involves checking and verifying the non-orthogonality of inputs to a current-mode logic technology output collector dot. Fig. 1 represents a version of current-mode logic gates configured with a collector ("C") dot. It shows two current-mode gates in output collector dot configuration. Arrows indicate possible current flow paths of each gate if non-orthogonality were not observed. The problem arises in that both gates are sourced by independent current elements with a common point of influence ("C" dot). If the dot terms from each gate were also allowed to be independent, a third logic state would be encountered.

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In-Stream Logic Simulation Non-Orthogonality Verification for Current- Mode Logic Technology Collector Dotting

Non-orthogonality between collector dots of current-mode logic technology is checked and verified by means of conventional logic and error induction. The method involves checking and verifying the non-orthogonality of inputs to a current-mode logic technology output collector dot. Fig. 1 represents a version of current-mode logic gates configured with a collector ("C") dot. It shows two current-mode gates in output collector dot configuration. Arrows indicate possible current flow paths of each gate if non-orthogonality were not observed. The problem arises in that both gates are sourced by independent current elements with a common point of influence ("C" dot). If the dot terms from each gate were also allowed to be independent, a third logic state would be encountered.

The logic technology normally performs logical operation by detecting the presence or absence of current flow at its output and associates these conditions with logical "1" and "0". The third state introduced by allowing output dot orthogonality is the possibility of the current elements of both gates influencing the "C" dot simultaneously. This not only complicates the logical operation, states of no current, one unit of current, and now the possibility of two units of current, but also may result in detrimental electrical effects in the actual circuitry. Offered is a conventional logic solution to finding and flagging this condition as in error, illustrated by means of the truth table (Fig. 2). In the truth table for the "C" dot of Fig. 1, Q represents an output term from conventional logic simulation of "Dot ANDed" terms. The non-orthogonal case passes with logical "0" at Q. Term Q' represents output from non-orthogonality verification simulation. The non-orthogonal case now results with logical "1" at Q'. Comparison of Q and Q' will indicate non-orthogonality errors as comparison faults.

The possibility for orthogonality violation occurs four times in the truth table (given by asterisks), where both W and Z are allowed to be on at the same time. However, only one case results in an actual error. Three of the cases given by "DC" (Don't Care) do not actually violate non-orthogonality in the dot, due to the state of the other terms in the equation. The non-orthogonality test is based on the premise that the logic has been successfully simulated and functionally accurate output patterns are available for future comparison. In addition, the test is based on the convention that current flow propagates logical "0". It should also be noted that the non-orthogonality of such configurations, as in Fig. 1, is only achievable...