Browse Prior Art Database

Generation of Multiple Single-Phase Outputs From a Single DCCS Decode Circuit

IP.com Disclosure Number: IPCOM000047794D
Original Publication Date: 1983-Dec-01
Included in the Prior Art Database: 2005-Feb-08
Document File: 2 page(s) / 49K

Publishing Venue

IBM

Related People

Cohen, ME: AUTHOR [+4]

Abstract

Multiple decode functions are provided for use in macros, off-chip drivers, etc. The article in [*] describes the use of current switches that are differentially connected to the inputs of a cascode decoder to provide high-speed operation at low power levels. A Differential Cascode Current Switch (DCCS) circuit of this nature requires both the true and complement phases of all input variables and provides the true and complement outputs for a desired function f. Here, the DCCS circuit provides a plurality of outputs if only the complement phase of the output functions is required. A typical DCCS decode circuit, such as the circuit in Fig. 1 which has a decode capability of "5", provides both phases of the output functions.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 87% of the total text.

Page 1 of 2

Generation of Multiple Single-Phase Outputs From a Single DCCS Decode Circuit

Multiple decode functions are provided for use in macros, off-chip drivers, etc. The article in [*] describes the use of current switches that are differentially connected to the inputs of a cascode decoder to provide high-speed operation at low power levels. A Differential Cascode Current Switch (DCCS) circuit of this nature requires both the true and complement phases of all input variables and provides the true and complement outputs for a desired function f. Here, the DCCS circuit provides a plurality of outputs if only the complement phase of the output functions is required. A typical DCCS decode circuit, such as the circuit in Fig. 1 which has a decode capability of "5", provides both phases of the output functions. To generate all 8 possible decodes of 3 variables requires 8 DCCS circuits; to generate all 16 possible decodes of 4 variables requires 16 DCCS; and to generate all possible decodes of 5 variables requires 32 DCCS circuits. In the design of LSI chips, there may exist macros, such as ROS and RAM or off- chip driver circuits, where both output phases are not required. If only the complement phase of the function is required, all possible decodes of 3, 4, 5 variables, etc., can be accomplished by a single DCCS circuit, as shown in Fig.
2. Reductions in power, input variable loading, wiring and components are realized. A number of decode functions can be developed in a si...