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Precharge Circuit for Static Random_access Memory Arrays

IP.com Disclosure Number: IPCOM000047796D
Original Publication Date: 1983-Dec-01
Included in the Prior Art Database: 2005-Feb-08
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Abstract

Static Random Access Memories (SRAMs) fall into two main categories: clocked and unclocked. Fig. 1 shows a representative SRAM consisting of columns of storage cells with a multiplexer at the bottom of each column to allow multiple data inputs to an input/output circuit. At the top of the columns is a precharge (or restore) circuit that returns both internal data lines in each column to the same positive potential. When one of the row select signals gets activated, it selects one storage cell per column. The cell discharges either the data or the data line, depending on the stored data polarity.

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Precharge Circuit for Static Random_access Memory Arrays

Static Random Access Memories (SRAMs) fall into two main categories: clocked and unclocked. Fig. 1 shows a representative SRAM consisting of columns of storage cells with a multiplexer at the bottom of each column to allow multiple data inputs to an input/output circuit. At the top of the columns is a precharge (or restore) circuit that returns both internal data lines in each column to the same positive potential. When one of the row select signals gets activated, it selects one storage cell per column. The cell discharges either the data or the data line, depending on the stored data polarity. Depending on the state of the column select signals, in this example there is a one-of-two selection, the data lines from either one or the other column are passed to the I/O circuits by either transistors T1-T2 or T3-T4 and their equivalent in the adjacent columns. In the case of a clocked SRAM, the precharge circuit devices are driven by an on-chip generated clock phase, as shown in Fig. 2. Unclocked precharge pullups are illustrated in Fig. 3. To get an adequate differential signal in the light of the continual charge injected into the data lines takes a more robust storage cell and, consequently, less density achievable and more power dissipation per bit than the clocked precharge memory devices. A third circuit type is available for CMOS SRAMS, as shown in, Fig. 4. Here, the column select signal, when positive, turns on transistors T1-T2, for example, while transistors T5-T6 are prevented from conduction by their positive gate potential. Transistors T3-T4 have a low potentia...