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Clock Generation Circuitry for Differential Cascode Current Switch LSSD Latches

IP.com Disclosure Number: IPCOM000047800D
Original Publication Date: 1983-Dec-01
Included in the Prior Art Database: 2005-Feb-08
Document File: 3 page(s) / 46K

Publishing Venue

IBM

Related People

Davis, JW: AUTHOR [+3]

Abstract

This circuitry generates A, B and C clock signals (clocks) for Level Sensitive Scan Design (LSSD) in Differential Cascode Current Switch (DCCS) technology, guarantees that the clocks are non-overlapping and provides a method so that overlapping, clocks may be enabled for LSSD testing. For the proper operation of LSSD clocks, the A and C clocks cannot overlap the B clock. During the LSSD flush test, both A and B clocks must be active simultaneously. This invention provides a means for generating the LSSD A clock, the LSSD B clock, and the LSSD C clock in the differential cascode current switch technology. It also provides a means to guarantee that the A and C clocks do not overlap the B clock, and it provides a means to override the non-overlapping clock feature during the LSSD flush test.

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Clock Generation Circuitry for Differential Cascode Current Switch LSSD Latches

This circuitry generates A, B and C clock signals (clocks) for Level Sensitive Scan Design (LSSD) in Differential Cascode Current Switch (DCCS) technology, guarantees that the clocks are non-overlapping and provides a method so that overlapping, clocks may be enabled for LSSD testing. For the proper operation of LSSD clocks, the A and C clocks cannot overlap the B clock. During the LSSD flush test, both A and B clocks must be active simultaneously. This invention provides a means for generating the LSSD A clock, the LSSD B clock, and the LSSD C clock in the differential cascode current switch technology. It also provides a means to guarantee that the A and C clocks do not overlap the B clock, and it provides a means to override the non-overlapping clock feature during the LSSD flush test. The circuitry disclosed here consists of three differential cascode current switch clock generation circuits and requires four input signal I/O pins for double-latch LSSD designs plus output test points on the clock circuitry, if desired, for testing the clock circuitry. The operation is as follows. The A and C clock circuits shown in Fig. 1 are responsive to an input "A- C oscillator" signal and either the A or C clock circuitry moves up and down with the same frequency as the A-C oscillator signal. A second input, LSSD test mode, is normally positive during system operation and allows the C clock to be operational and disables the A clock. During testing, however, this input signal may be pulled down by the tester so that the A clock is operational and the C clock is disabled. The B clock outputs from the B clock circuit shown in Fig. 2 are put through translators and used to delay the leading edge of the A and C clocks so that these clocks cannot occur while the B clock is still active. This control from the B clock can be overridden by the "Clock Overlap" mode signal I/O for the A clock during the flush test but the override is not required for the C clock for double-latch designs. The operation of a basic DCCS circuit allows current to flow through only one path of a tree. A 5-level DCCS circuit path is defined by a series of 1 to 5 transistors all of which must have positive inputs. Fig. 1 shows the A clock and C clock generation, and operates as follows. If the scan mode input signal is active, current will flow through transistor 2 to allow A clock generation; otherwise, if scan mode is not present, the A clock will always be held off by current flow through transistor 1. When transistor 2 is conducting, the clock overlap input is test...