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Fully Passivated Transistor Process

IP.com Disclosure Number: IPCOM000047824D
Original Publication Date: 1983-Dec-01
Included in the Prior Art Database: 2005-Feb-08
Document File: 2 page(s) / 55K

Publishing Venue

IBM

Related People

Dockerty, RC: AUTHOR

Abstract

A poly base, poly emitter process is described that is simpler than the previous processes. The resulting structure has an oxide sidewall and full passivation against ionic impurities. Any conventional process can be followed up to the underlay deposition, as shown in Fig. 1. The proposed process follows: 1) Deposit underlay nitride (NI). 2) Apply resist (PR). 3) Reactive ion etch (RIE) nitride and oxide in CF4 (Fig. 2). 4) Strip resist. 5) Base poly deposition. 6) Poly reox (OI). 7) Extrinsic base implant. 8) Nitride overcoat (NII). 9) Apply next level PR - defines inner and outer edges of base poly (Fig. 3). 10) RIE nitride (NII) and strip PR. 11) Wet etch oxide (OI). 12) RIE base poly (Fig. 4). 13) Next level PR (resist covers emitter opening). 14) Poly filament etch (Fig. 5). 15) Strip PR.

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Fully Passivated Transistor Process

A poly base, poly emitter process is described that is simpler than the previous processes. The resulting structure has an oxide sidewall and full passivation against ionic impurities. Any conventional process can be followed up to the underlay deposition, as shown in Fig. 1. The proposed process follows: 1) Deposit underlay nitride (NI). 2) Apply resist (PR). 3) Reactive ion etch (RIE) nitride and oxide in CF4 (Fig. 2). 4) Strip resist. 5) Base poly deposition. 6) Poly reox (OI). 7) Extrinsic base implant. 8) Nitride overcoat (NII). 9) Apply next level PR - defines inner and outer edges of base poly (Fig. 3). 10) RIE nitride (NII) and strip PR.
11) Wet etch oxide (OI). 12) RIE base poly (Fig. 4). 13) Next level PR (resist covers emitter opening). 14) Poly filament etch (Fig. 5).
15) Strip PR. 16) Grow 500 Si02 (OII). 17) Low pressure chemical vapor deposit (LPCVD) oxide sidewall deposition (OIII) (Fig. 6). 18) RIE LPCVD oxide and 500 thermal oxide. 19) Deposit emitter poly (Fig. 7), and continue with additional processing. All contacts will be nitride defined except for the emitter poly contact. The contact openings will be through:

(Image Omitted)

The oxide sidewall will reduce hot electron effects at the emitter-base junction. Fig. 8 shows complete passivation of the emitter-base junction. NI passivates the entire chip except in the device base area (F level opening) and contact areas.

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