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Multi-Port RAM Cell Structure

IP.com Disclosure Number: IPCOM000047827D
Original Publication Date: 1983-Dec-01
Included in the Prior Art Database: 2005-Feb-08
Document File: 2 page(s) / 53K

Publishing Venue

IBM

Related People

Shen, MN: AUTHOR

Abstract

A single-port random-access memory (RAM) cell is shown in Fig. 1. The transistors T1, T2 and resistors R1, R2, R3 comprise the basic cross-coupled flip-flop RAM cell. W is the Write line, and DI is the Data In line. R is for the Read line, and SA is connected to the Sense Amplifier. When W is at up level, the state of the RAM cell can be changed by the voltage levels at the DI node. The emitter of the T2 is connected to the DI node, so when the Write node W returns to the normal down level, the DI node will hold the RAM cell stable. When the RAM cell is sensed, the Read line R is set to the up level, and the node voltage at node C1 can thus be sensed by the Sense Amplifier (not shown). Fig. 2 and Fig. 3 show two variations of a multi-port RAM cell where a 2R, 2W structure is depicted. In Fig.

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Multi-Port RAM Cell Structure

A single-port random-access memory (RAM) cell is shown in Fig. 1. The transistors T1, T2 and resistors R1, R2, R3 comprise the basic cross-coupled flip-flop RAM cell. W is the Write line, and DI is the Data In line. R is for the Read line, and SA is connected to the Sense Amplifier. When W is at up level, the state of the RAM cell can be changed by the voltage levels at the DI node. The emitter of the T2 is connected to the DI node, so when the Write node W returns to the normal down level, the DI node will hold the RAM cell stable. When the RAM cell is sensed, the Read line R is set to the up level, and the node voltage at node C1 can thus be sensed by the Sense Amplifier (not shown). Fig. 2 and Fig. 3 show two variations of a multi-port RAM cell where a 2R, 2W structure is depicted. In Fig. 2, DI1 (DI2) and DI1 (DI2) are the in-phase and out-of-phase outputs of the Data In buffer DI1(DI2) (not shown). W1 and W2 are two separate Write control lines. When W1 or W2 is at the up level, the cell is ready for write operation. (The system design prevents W1 and W2 being at the up level for the same address at the same time.) The sense amplifier (SA1 or SA2) can sense the node voltage C1 when R1 and/or R2 are at up level. Fig. 3 shows another variation of the 2R, 2W RAM cell. When the Write lines W1 and W2 are at the up level, the read operation can be executed by raising R1 and/or R2 to an up level. When either W1 or W2 is at down level,...