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Dynamic Testing of Multiple Embedded Arrays on the Same Chip by an Array Tester With Limited I/O Capability

IP.com Disclosure Number: IPCOM000047833D
Original Publication Date: 1983-Dec-01
Included in the Prior Art Database: 2005-Feb-08
Document File: 2 page(s) / 48K

Publishing Venue

IBM

Related People

Shen, MN: AUTHOR

Abstract

The disclosed dynamic testing technique of multiple embedded arrays on the same chip by a limited I/O array tester can be illustrated with the following example: 1) Limitation of array tester: Total I/O's(signal) = 96 Maximum Data In(DI) or Data Out(DO) = 36 2) Embedded arrays: 16 X 45 with byte control of 18, 18 and 9 bits, i.e., 16 X 18, 16 X 18, 16 X 9. Signal I/O's for these arrays: 4 address lines 3 R/W lines 45 DI's 45 DO's Total Signal I/O's = 97 This violates the limitations set forth in (1).

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Dynamic Testing of Multiple Embedded Arrays on the Same Chip by an Array Tester With Limited I/O Capability

The disclosed dynamic testing technique of multiple embedded arrays on the same chip by a limited I/O array tester can be illustrated with the following example: 1) Limitation of array tester: Total I/O's(signal) = 96

Maximum Data In(DI) or Data Out(DO) = 36 2) Embedded arrays:

16 X 45 with byte control of 18, 18 and 9 bits,

i.e.,

16 X 18, 16 X 18, 16 X 9.

Signal I/O's for these arrays:

4 address lines

3 R/W lines

45 DI's

45 DO's

Total Signal I/O's = 97

This violates the limitations set forth in (1). 3) Dynamic testing technique: Let us call 16 X 18 = Array A

16 X 18 = Array B

16 X 9 = Array C The testing technique, in accordance with the example, is illustrated in Fig. 1. The dotting scheme is as follows: a) Dot the 9 DI's of Array A with the 9 DI's of Array C. b) Dot the 9 DO's of Array B with the 9 DO's of Array

C. c) Total signal I/O's required to test arrays A, B and

C:

4 address lines

3 R/W control lines

36 DI's / 36 DO's

79 lines total This satisfies the limitations in paragraph (1). d) Write all 's into Array C and keep Array C in READ mode. e) Complete the testing of Arrays A and B. f) Write allø 's into Array B and keep Array B in READ mode. g) Complete the testing of Array C. In the embedded array test scheme depicted in Fig. 2, there is an AI gate 10 connected between sense amplifier 11 and driver 9. This is the reason ø's are written into Array...