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LVI Enable Circuit

IP.com Disclosure Number: IPCOM000047837D
Original Publication Date: 1983-Dec-01
Included in the Prior Art Database: 2005-Feb-08
Document File: 2 page(s) / 49K

Publishing Venue

IBM

Related People

Mosley, J: AUTHOR [+2]

Abstract

The Low Voltage Inverter (LVI) logic circuit shown in Fig. 1 is described in detail in [*]. The circuit in Fig. 2 extends the logic capability of the LVI logic circuit. The enable function turns off the logic gate so that input signals to IN1 and IN2 would be ignored. The output of the circuit remains at a logic high level. To disable the logic circuit, a special logic high level, which is higher than the normal LVI logic high level, is applied to the enable line. This signal turns on transistor T3 which in turn does not permit transistors T1 or T2 to turn on regardless of the normal LVI logic levels applied to either input IN1 or IN2. Therefore, the output signal remains at a logic level high.

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LVI Enable Circuit

The Low Voltage Inverter (LVI) logic circuit shown in Fig. 1 is described in detail in [*]. The circuit in Fig. 2 extends the logic capability of the LVI logic circuit. The enable function turns off the logic gate so that input signals to IN1 and IN2 would be ignored.

The output of the circuit remains at a logic high level. To disable the logic circuit, a special logic high level, which is higher than the normal LVI logic high level, is applied to the enable line. This signal turns on transistor T3 which in turn does not permit transistors T1 or T2 to turn on regardless of the normal LVI logic levels applied to either input IN1 or IN2. Therefore, the output signal remains at a logic level high. Applying a normal LVI logic low level to the enable input returns the circuit to normal LVI circuit operation in which signals applied to inputs IN1 and IN2 determine output logic level. Fig. 3 is an example of a circuit which generates the special logic high level for the input enable in Fig. 2. The circuit operates similar to the LVI logic circuit in Fig. 1. Note that the circuit in Fig. 3 has resistor Rout of Fig. 1 removed and a pull-up resistor added between VC and Out. These changes generate a higher than normal LVI logic high level while maintaining a similar LVI logic low level. References (*) John G. Posa, "Low-V inverter logic outperforms ECL yet saves saves power," Electronics 4, 41-42 (February 1981). Also, see U.S. Patent 4,283,640.

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