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Browse Prior Art Database

Multi-Port RAM Cell

IP.com Disclosure Number: IPCOM000047845D
Original Publication Date: 1983-Dec-01
Included in the Prior Art Database: 2005-Feb-08
Document File: 2 page(s) / 40K

Publishing Venue

IBM

Related People

Shen, MN: AUTHOR

Abstract

A single-port random-access memory (RAM) cell configuration is shown in Fig. 1. A multi-port, two-read, two-write, (2R-2W) RAM cell is shown in Fig. 2. Referring to Fig. 2, when a read line (R1 or R2) is UP, the cell is conditioned for a read operation, and when a write line (W1 or W2) is UP, the cell is conditioned for a write operation. When the write line W1 is UP, the data (1 or 0) on Data In 1(DI1) line will be written in the RAM cell. When write line W2 is UP, the data (1 or 0) on data IN 2(DI2) line will be written into the RAM cell. The read operation is controlled by the potential at nodes R1 and R2. Whenever R1 or R2 is UP, the information stored in the cell is sensed by one of the sense amplifiers SA1 or SA2 (not shown).

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Multi-Port RAM Cell

A single-port random-access memory (RAM) cell configuration is shown in Fig.
1. A multi-port, two-read, two-write, (2R-2W) RAM cell is shown in Fig. 2. Referring to Fig. 2, when a read line (R1 or R2) is UP, the cell is conditioned for a read operation, and when a write line (W1 or W2) is UP, the cell is conditioned for a write operation. When the write line W1 is UP, the data (1 or 0) on Data In 1(DI1) line will be written in the RAM cell. When write line W2 is UP, the data (1 or 0) on data IN 2(DI2) line will be written into the RAM cell. The read operation is controlled by the potential at nodes R1 and R2. Whenever R1 or R2 is UP, the information stored in the cell is sensed by one of the sense amplifiers SA1 or SA2 (not shown).

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