Browse Prior Art Database

Compare Scheme for Schottky-Coupled Cell That Allows Compare While Write

IP.com Disclosure Number: IPCOM000047846D
Original Publication Date: 1983-Dec-01
Included in the Prior Art Database: 2005-Feb-08
Document File: 2 page(s) / 48K

Publishing Venue

IBM

Related People

Buscaglia, CU: AUTHOR

Abstract

Previous compare functions embedded on a directory array chip compare array data to compare input data when the array is in a read mode; however, compare becomes invalid during a write operation. The scheme disclosed compares array data being read to compare input data and also write data in (data being written into the array) to compare input data during a write operation. Reference is made to the drawing. When the cell is written, one bit line is pulled up (depending on write data polarity) by the bit driver while the upper word line (UWL) and lower word line (LWL) are pulled down. To write a zero bit line, 0/ is pulled high, which shuts off T1 in the sense amplifier and the emitter of T3 goes high, turning on T1 in the compare circuit.

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Compare Scheme for Schottky-Coupled Cell That Allows Compare While Write

Previous compare functions embedded on a directory array chip compare array data to compare input data when the array is in a read mode; however, compare becomes invalid during a write operation. The scheme disclosed compares array data being read to compare input data and also write data in (data being written into the array) to compare input data during a write operation. Reference is made to the drawing. When the cell is written, one bit line is pulled up (depending on write data polarity) by the bit driver while the upper word line (UWL) and lower word line (LWL) are pulled down. To write a zero bit line, 0/ is pulled high, which shuts off T1 in the sense amplifier and the emitter of T3 goes high, turning on T1 in the compare circuit. With T1 on and CDC high and CDT low (0/ compare input data) T6 turns on holding CMP OUT low, signaling a good compare. With CDC low and CDT high (1 compare input data) T4 would be on allowing CMP OUT to go high, signaling a bad compare. Therefore, "write data in" which appears on the bit lines is compared against "compare data in" when the chip is in the write mode. After a zero is written, node 1 of the cell is high. When the cell is read, the LWL is pulled down and T2 in the cell draws current through its I/O Schottky diode. T2 of the sense amplifier sources this current so the emitter of T4 is low. T1 in the cell and its I/O Schottky diode are off so the...