Browse Prior Art Database

Write Select Scheme for Schottky Coupled Cell With Early Upper Word-Line Deselect

IP.com Disclosure Number: IPCOM000047847D
Original Publication Date: 1983-Dec-01
Included in the Prior Art Database: 2005-Feb-08
Document File: 2 page(s) / 70K

Publishing Venue

IBM

Related People

Buscaglia, CU: AUTHOR [+2]

Abstract

High end Schottky-coupled cell array designs incorporate a high speed bit driver that enhances write time. During a write operation the Upper Word Line (UWL) is pulled down, making the cell unstable, while a bit line is pulled up, writing the cell. At the end of a write cycle the UWL must come back up before the bit line comes down in order to retain data. Bringing the bit line up sooner enhances write time. However, if it is brought down earlier relative to the UWL, a potential data retention problem exists. In order to take advantage of a faster bit driver the write select scheme (which features an early UWL deselect) of Fig. 1 may be utilized. The write select scheme must enable one out of eight UWLs on all row addresses plus select one group out of eight groups of bit drivers. Referring to Fig.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 78% of the total text.

Page 1 of 2

Write Select Scheme for Schottky Coupled Cell With Early Upper Word-Line Deselect

High end Schottky-coupled cell array designs incorporate a high speed bit driver that enhances write time. During a write operation the Upper Word Line (UWL) is pulled down, making the cell unstable, while a bit line is pulled up, writing the cell. At the end of a write cycle the UWL must come back up before the bit line comes down in order to retain data. Bringing the bit line up sooner enhances write time. However, if it is brought down earlier relative to the UWL, a potential data retention problem exists. In order to take advantage of a faster bit driver the write select scheme (which features an early UWL deselect) of Fig. 1 may be utilized. The write select scheme must enable one out of eight UWLs on all row addresses plus select one group out of eight groups of bit drivers. Referring to Fig. 1, the write byte select (WBS) lines are set up prior to the write clock coming down. One WBS is low depending on which subarray is to be written. When the write clock goes low initiating the write operation, the selected WBS gate enables the appropriate UWL driver and group of bit drivers. The bit line rises and the UWL falls at the same time, as can be seen in the waveforms of Fig. 2. When the write clock comes back up, the UWL driver is immediately disabled via T2 being directly connected to the R/W receiver. The bit line remains high for a gate delay after the UWL comes up (see Fig. 2...