Browse Prior Art Database

Multi-Chip Planar Memory Package

IP.com Disclosure Number: IPCOM000047848D
Original Publication Date: 1983-Dec-01
Included in the Prior Art Database: 2005-Feb-08
Document File: 2 page(s) / 63K

Publishing Venue

IBM

Related People

Hubacher, EM: AUTHOR

Abstract

This proposal provides a low-cost memory packaging scheme that interconnects two or more partially good chips to form a memory module. A single planar (MC, paste, etc.) substrate part number personalized after chip join is employed to provide the interconnection of the bit or address lines. This disclosure employs chips designed so that either the address or the data lines are connected to C4 pads in a contiguous arrangement. The arrangement must ensure the address (or data for data in/out partially good chip) bus lines are all adjacent to one another when wired on the planar substrate (Figs. 1, 2). The chip C4 design must also be spaced sufficiently to permit at least one substrate line to be run between the pads. The substrate on which the chips will be joined contains a pattern, as shown in Fig. 3.

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Multi-Chip Planar Memory Package

This proposal provides a low-cost memory packaging scheme that interconnects two or more partially good chips to form a memory module. A single planar (MC, paste, etc.) substrate part number personalized after chip join is employed to provide the interconnection of the bit or address lines. This disclosure employs chips designed so that either the address or the data lines are connected to C4 pads in a contiguous arrangement. The arrangement must ensure the address (or data for data in/out partially good chip) bus lines are all adjacent to one another when wired on the planar substrate (Figs. 1, 2). The chip C4 design must also be spaced sufficiently to permit at least one substrate line to be run between the pads. The substrate on which the chips will be joined contains a pattern, as shown in Fig. 3. Only two chips are shown for illustration purposes; however, additional chips could be placed utilizing a similar interconnection scheme. To illustrate the fabrication process, chips electrically tested at wafer level are sorted for one bad address (or bit). For example, a 64K x 1 is sorted for 32K x 1's (or a 1K x 10 is sorted for 1K x 9's). These chips would then be catalogued for the defective address (or bit) via laser or ink marking the back. The chips are then joined on the substrate shown in Fig. 3. For illustrative purposes, two 64K x 1 chips, each with one bad address, are shown. Using the part number identification marked o...