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Emitter Follower Reverse Bias Clamp

IP.com Disclosure Number: IPCOM000047850D
Original Publication Date: 1983-Dec-01
Included in the Prior Art Database: 2005-Feb-08
Document File: 2 page(s) / 40K

Publishing Venue

IBM

Related People

Gaudenzi, GJ: AUTHOR [+2]

Abstract

A conventional non-Darlington output stage of a three-state push-pull driver is illustrated in Fig. 1. During high impedance operation, the base of the emitter follower output transistor TU must be biased at approximately .5 V to insure no current flow from TU. Because of the three-state function, this driver may be dotted with other drivers such that output voltage VO may be at a logical 1 level (N5.0 V). The reverse bias across the emitter-base junction of TU is =VRB=5.0-.5=4.5 V. A reverse bias >2.8 V will result in significant beta degradation of transistor TU . AS beta of the output transistor degrades, AC and DC functionality will be adversely affected. A clamp circuit designed to control the maximum reverse bias across the output transistor during three-state operation is included in the driver circuit shown in Fig.

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Emitter Follower Reverse Bias Clamp

A conventional non-Darlington output stage of a three-state push-pull driver is illustrated in Fig. 1. During high impedance operation, the base of the emitter follower output transistor TU must be biased at approximately .5 V to insure no current flow from TU. Because of the three-state function, this driver may be dotted with other drivers such that output voltage VO may be at a logical 1 level (N5.0 V). The reverse bias across the emitter-base junction of TU is =VRB=5.0-.5=4.5 V. A reverse bias >2.8 V will result in significant beta degradation of transistor TU . AS beta of the output transistor degrades, AC and DC functionality will be adversely affected. A clamp circuit designed to control the maximum reverse bias across the output transistor during three-state operation is included in the driver circuit shown in Fig. 2 (TC, RCC and RC). During three state operation, node T is at a logical 1 level causing nodes 1 and 3 to be at N.5 V, forcing the driver into the high impedance state. Referring to Fig. 2, the voltage across output transistor TU can be calculated as follows: VO - (IB(TC) X RCC) - VBE(TC) - (IE(TC) X RC) = .5 V where IE(TC) = (B+1) * IB(TC) for RCC = RC = 5.0K, Beta = 75, VBE(TC) N.8 V and VO = 5.0 V Solving for IB, IB = .0096 ma The voltage across the emitter-base junction of TU = VRB = V0-V2

VRB = 5.0 -(5.0 - IB(TC) * RCC - .8)

VRB = .85 V VRB is well within the 2.8 V reverse bias limit.

The Fig. 2 circuit...