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Browse Prior Art Database

DTL Compare Circuit

IP.com Disclosure Number: IPCOM000047859D
Original Publication Date: 1983-Dec-01
Included in the Prior Art Database: 2005-Feb-08
Document File: 3 page(s) / 31K

Publishing Venue

IBM

Related People

Andersen, JE: AUTHOR

Abstract

Substantial speed improvement in a compare circuit is achieved by elimination of the current switch typically employed in the two-transistor compare circuit arrangements of the prior art. In the present scheme, the compare logic circuit employs two transistors and four diodes. Present transistor compare logic circuits normally comprise a 1 ma cascoded current-switch emitter follower with a delay time of approximately 800 picoseconds. In typical system arrangements, one of the critical timing parameters is the sum of the array access time and the compare time through the directory chip. In the exclusive-OR compare logic gate shown in the figure, this sum is reduced by approximately 0.5 nanosecond.

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DTL Compare Circuit

Substantial speed improvement in a compare circuit is achieved by elimination of the current switch typically employed in the two-transistor compare circuit arrangements of the prior art. In the present scheme, the compare logic circuit employs two transistors and four diodes. Present transistor compare logic circuits normally comprise a 1 ma cascoded current-switch emitter follower with a delay time of approximately 800 picoseconds. In typical system arrangements, one of the critical timing parameters is the sum of the array access time and the compare time through the directory chip.

In the exclusive-OR compare logic gate shown in the figure, this sum is reduced by approximately 0.5 nanosecond. The delay in the DTL circuit arrangement of the figure is reduced by more than 500 pecoseconds over the cascoded current-switch emitter follower arrangement described above. The speed improvement is attributed to the elimination of the current switch which requires the switching of two transistors to change the output (charging and discharging Ccb and Ccs in the current switch and Ccb on a base of the emitter follower). By eliminating the current switches, the associated capacitances on the bases of the emitter followers are eliminated. In the compare logic gate of the figure, when the array content and compare input match, a successful compare is achieved and indicated by a low level on the compare output. The operation of the DTL gate is as follows: Case 1 Successful Compare Array input = 1 (Sd = +0.2 V, S1 = -0.3 V) Compare input = 1 (CDIC = -0.3 V, CDIT = +0.2 V) The cathodes of D2 and D6 pull low and become forward biased. D1 and D5 remain off since their cathodes are high. D2 and D6 pull
0.85 mA through R1 and R2, droppin...