Browse Prior Art Database

Byte Select Circuit for Low-Power Random-Access Memory

IP.com Disclosure Number: IPCOM000047864D
Original Publication Date: 1983-Dec-01
Included in the Prior Art Database: 2005-Feb-08
Document File: 2 page(s) / 40K

Publishing Venue

IBM

Related People

Denis, B: AUTHOR [+2]

Abstract

The byte select circuit shown in the drawing allows the dissipated power in a memory to be reduced, by preventing the current from flowing in the bit line of non-selected byte cells. In a random-access memory (RAM), comprising a matrix of HARPNP cells or Harper cells, a current is permanently flowing in the right and left bit lines RBL and LBL which are connected to the cells of the matrix columns. The byte select circuit has for a function the switching off of the current in the right and left bit line transistors TBR and TBL of the bit lines which are not selected, when a row of cells is accessed. It comprises a byte decoder circuit including true/complement generators (TCGs), and a byte Schottky barrier diode (SBD) matrix decoder.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 70% of the total text.

Page 1 of 2

Byte Select Circuit for Low-Power Random-Access Memory

The byte select circuit shown in the drawing allows the dissipated power in a memory to be reduced, by preventing the current from flowing in the bit line of non-selected byte cells. In a random-access memory (RAM), comprising a matrix of HARPNP cells or Harper cells, a current is permanently flowing in the right and left bit lines RBL and LBL which are connected to the cells of the matrix columns. The byte select circuit has for a function the switching off of the current in the right and left bit line transistors TBR and TBL of the bit lines which are not selected, when a row of cells is accessed. It comprises a byte decoder circuit including true/complement generators (TCGs), and a byte Schottky barrier diode (SBD) matrix decoder. When the row of cells stores eight bytes of n data bits, three TCGs are provided which receive the byte address A0, A1, A2 of the byte to be selected in a row of cells. In the SBD decoder matrix, depending upon the address configuration, the three SBD diodes in only one column are OFF, whereas in the other column at least one diode is ON. When at least one cathode of the diode D2i, D1i, D0i is at a low level, (0.3 V) in the deselected state, current IR flows into the forward biased diodes, and the potential at node 1 is clamped to a voltage level which makes diode D4i and transistor T1i OFF. The n pairs of bit lines transistors TBLi and TBRi connected to this current mirror refer...