Browse Prior Art Database

Bus System

IP.com Disclosure Number: IPCOM000047869D
Original Publication Date: 1983-Dec-01
Included in the Prior Art Database: 2005-Feb-08
Document File: 2 page(s) / 59K

Publishing Venue

IBM

Related People

Blum, A: AUTHOR

Abstract

The bus system shown in Fig. 1 consists of the bus units I to III with independent internal clock generators (not shown). In addition, the three bus units, which are interconnected by an address/data bus, may have a common clock system which emits time-skewed clocks, so that the three units have to work asynchronously. According to bus busy conditions, one of the bus units is granted access to the address/data bus by a bus arbitration unit. A line 11 for serial arbitration is arranged between bus units I, II and III. The lower part of the circuit diagram shows two clock lines 4 and 5 which control the information exchange between bus units I, II and III through the address/data bus. In contrast to previous bus systems, the present system is controlled in response to pulses 1 and 2 on lines 4 and 5 (Fig. 2).

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Bus System

The bus system shown in Fig. 1 consists of the bus units I to III with independent internal clock generators (not shown). In addition, the three bus units, which are interconnected by an address/data bus, may have a common clock system which emits time-skewed clocks, so that the three units have to work asynchronously. According to bus busy conditions, one of the bus units is granted access to the address/data bus by a bus arbitration unit. A line 11 for serial arbitration is arranged between bus units I, II and III. The lower part of the circuit diagram shows two clock lines 4 and 5 which control the information exchange between bus units I, II and III through the address/data bus. In contrast to previous bus systems, the present system is controlled in response to pulses 1 and 2 on lines 4 and 5 (Fig. 2). Through line 4 (VAL-CLOCK), for example, a pulse 1 is fed from bus unit I to bus unit II. At that time, the address or the information on the address/data bus is valid, depending on what is being handled. Having been received by bus unit II, pulse 1 causes the information - an address or a data word - to be latched. Subsequently, pulse 1 is used in a similar manner for further transfer steps. For this purpose, it is switched through (propagated) and transferred on line 5 (ACK-CLOCK) after the address has been decoded. Thus, the information from bus unit II may be transferred to bus unit III or be returned to bus unit I. In a similar manner, acknowle...