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Mp/Dynamic Memory Synchronizer

IP.com Disclosure Number: IPCOM000047874D
Original Publication Date: 1983-Dec-01
Included in the Prior Art Database: 2005-Feb-08
Document File: 3 page(s) / 73K

Publishing Venue

IBM

Related People

Babcock, AS: AUTHOR [+2]

Abstract

This article describes a sequential logic arrangement for providing synchronization between a microprocessor and a dynamic memory which requires refresh. The synchronizer is shown in Fig. 1, and the timing diagram, shown in Fig. 2, illustrates its operation, for example, when a request for a refresh cycle occurs between the rise and fall of an oscillator pulse. Initially, let it be assumed that all of the flip-flops 2, 4, 10, 12 and 30 and the latch 26 are held in their OFF state due to negative signals maintained at their reset inputs. The fact that the sequential flip-flops 2, 4, 10 and 12 are in their OFF state is detected by the AND invert circuit 24 to maintain a negative signal, via the ALL FF OFF line and NOR invert circuit 34 on the first leg of the NAND circuit 38.

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Mp/Dynamic Memory Synchronizer

This article describes a sequential logic arrangement for providing synchronization between a microprocessor and a dynamic memory which requires refresh. The synchronizer is shown in Fig. 1, and the timing diagram, shown in Fig. 2, illustrates its operation, for example, when a request for a refresh cycle occurs between the rise and fall of an oscillator pulse. Initially, let it be assumed that all of the flip-flops 2, 4, 10, 12 and 30 and the latch 26 are held in their OFF state due to negative signals maintained at their reset inputs. The fact that the sequential flip-flops 2, 4, 10 and 12 are in their OFF state is detected by the AND invert circuit 24 to maintain a negative signal, via the ALL FF OFF line and NOR invert circuit 34 on the first leg of the NAND circuit 38. However, the absence of positive signals on the +REFRESH CYC, +MEM CYC and +MP MEM SEL lines deconditions the NAND circuit 38 via the NOR circuit 36 to maintain a negative signal on the +START CLOCK line. When the memory requires a refresh cycle, a positive signal is applied to the +REFRESH CYC line where it is inverted by inverter 31 to a negative signal and applied to render the NAND circuit 38 effective, via the NOR invert circuits 34 and 36, to apply a positive signal to the START CLOCK line which removes the reset condition for the flip-flops 2 and 4. The trailing edge of the oscillator pulse following the application of the positive signal to +REFRESH CYC line is effective to turn flip- flop 4 to the ON state which, in being turned ON, conditions the trigger 12 for being turned ON. The positive shift of the next succeeding oscillating pulse is inverted by inverter 1 to a negative signal which is applied to turn ON flip-flops 2 and 12. Flip-flop 12, in being turned ON, applies a positive signal to the OR invert circuit 6 where it is inverted to a negative signal and applied to maintain flip-flop 10 in the reset or OFF state. The positive signal output of the flip-flop 12 is also applied to the negative inverter 20 which, in turn, deconditions the AND invert circuit 24 to apply a positive signal to the -ALL FF OFF line to thereby remove the negative signal from the reset input of the latch 26. The positive signal from the flip-flop 12 in combination with the positive signal from the oscillator renders the AND circuit 14 effective to apply a positive signal to the OR invert circuit 22 to initiate the first gated oscillator pulse to the memory. The state of the synchronizer will remai...