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And Gate Driver

IP.com Disclosure Number: IPCOM000047884D
Original Publication Date: 1983-Dec-01
Included in the Prior Art Database: 2005-Feb-08
Document File: 2 page(s) / 29K

Publishing Venue

IBM

Related People

Boyle, DH: AUTHOR [+2]

Abstract

An AND gate circuit is shown in the figure, employing "natural threshold" FET devices 4, 5 and 7. A first input signal A is applied to the enhancement-mode device 2 and the natural device 5. The input signal B is applied to the enhancement-mode device 3 and the natural device 4. When both A and B are up, the output node between devices 1 and 2 goes to substantially ground potential and turns off device 8 in the output stage. Enhancement-mode device 6 is also turned off, while natural devices 4 and 5 are on, thereby raising the potential at the node between devices 5 and 6, which is applied to the gate of the natural device 7 and the gate of the depletion-mode device 9.

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And Gate Driver

An AND gate circuit is shown in the figure, employing "natural threshold" FET devices 4, 5 and 7. A first input signal A is applied to the enhancement-mode device 2 and the natural device 5. The input signal B is applied to the enhancement-mode device 3 and the natural device 4. When both A and B are up, the output node between devices 1 and 2 goes to substantially ground potential and turns off device 8 in the output stage. Enhancement-mode device 6 is also turned off, while natural devices 4 and 5 are on, thereby raising the potential at the node between devices 5 and 6, which is applied to the gate of the natural device 7 and the gate of the depletion-mode device 9. This applies a quickly rising signal at the output node between devices 7 and 8 which has a full up-level of VDD which is maintained by the depletion-mode device 9. The up- level on the output node between devices 7 and 8 occurs only when both A and B are up. Any other combination of A and B results in a ground potential output on the node between devices 7 and 8. Thus, the AND logical function is achieved. Note that the upper branch consisting of devices 1, 2 and 3 performs the NAND function, and the lower branch consisting of devices 4, 5 and 6 performs the AND function.

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