Browse Prior Art Database

Rotational Frequency Detector

IP.com Disclosure Number: IPCOM000047905D
Original Publication Date: 1983-Dec-01
Included in the Prior Art Database: 2005-Feb-08
Document File: 2 page(s) / 52K

Publishing Venue

IBM

Related People

Coburn, RL: AUTHOR [+3]

Abstract

A rotational frequency detector is formed from an emitter-coupled VCO (voltage-controlled oscillator), a limiting amplifier, three D-type flip-flops and associated combinatorial logic circuits. The rotational frequency detector is used as a frequency acquisition aid in a phase-locked loop. Fig. 1 shows a logic diagram of the rotational frequency detector. The limiting amplifier converts the triangular quadrature phase signal across the external timing capacitor of the VCO into a square pulse. The VCO also generates a zero phase signal. In operation, the D flip-flop (F/F) 1 is used to generate a positive transition at G every time positive transitions of the reference signal (fr) rotate from quadrant A to D and from quadrant B to C (Figs. 2 and 3).

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Rotational Frequency Detector

A rotational frequency detector is formed from an emitter-coupled VCO (voltage-controlled oscillator), a limiting amplifier, three D-type flip-flops and associated combinatorial logic circuits. The rotational frequency detector is used as a frequency acquisition aid in a phase-locked loop. Fig. 1 shows a logic diagram of the rotational frequency detector. The limiting amplifier converts the triangular quadrature phase signal across the external timing capacitor of the VCO into a square pulse. The VCO also generates a zero phase signal. In operation, the D flip-flop (F/F) 1 is used to generate a positive transition at G every time positive transitions of the reference signal (fr) rotate from quadrant A to D and from quadrant B to C (Figs. 2 and 3). The logical state of the quadrature signal at these instants is latched into D F/F 2. A logical 1 is latched in by a A to D rotation and a logical 0 is latched in by a B to C rotation. When a logical 0 is stored in D F/F 2, the signal at C is the same as the quadrature signal (neglecting gate propagation delay). Therefore, C is at a logical level 1 when rotations occur from quadrant D to A. A positive transition generated at A by the very first rotation from quadrant D to A (after the last rotation from quadrant B to
C) generates a pulse at the output of D F/F 3; the pulse at D in turn generates a pulse at pump-down output F. D F/F 3 is reset by the negative cycle immediately following the...