Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Dynamic L1/Static L2 Merged CMOS Register Circuits

IP.com Disclosure Number: IPCOM000047998D
Original Publication Date: 1983-Dec-01
Included in the Prior Art Database: 2005-Feb-08
Document File: 3 page(s) / 46K

Publishing Venue

IBM

Related People

Thoma, NG: AUTHOR

Abstract

Circuits are described that provide the capability to include fairly dense Shift Register Latch (SRL) circuits on a cascode voltage switch masterslice. The circuits include a dynamic L1 - static L2 register latch that is well adapted as a macro element in a cascode logic system. A circuit masterslice customarily includes a brickwalled set of circuits. For example, these may be differential NMOS transistor pairs with a shared source diffusion. Any circuit implemented has to have a circuit topology that uses the available transistors in pairs; otherwise, there will be a layout inefficiency. Also, the limited number of P-load devices forces the best designs to fit the input multiplexing or logic functions into a "tree" format, which may be the intent in the use of the masterslice.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 52% of the total text.

Page 1 of 3

Dynamic L1/Static L2 Merged CMOS Register Circuits

Circuits are described that provide the capability to include fairly dense Shift Register Latch (SRL) circuits on a cascode voltage switch masterslice. The circuits include a dynamic L1 - static L2 register latch that is well adapted as a macro element in a cascode logic system. A circuit masterslice customarily includes a brickwalled set of circuits. For example, these may be differential NMOS transistor pairs with a shared source diffusion. Any circuit implemented has to have a circuit topology that uses the available transistors in pairs; otherwise, there will be a layout inefficiency.

Also, the limited number of P-load devices forces the best designs to fit the input multiplexing or logic functions into a "tree" format, which may be the intent in the use of the masterslice. A bipolar chip has been considered which has a merged L1/L2 latch designed to fit inside a single tree accounting area of ten differential pairs. The circuits here do likewise for circuits utilizing Complementary Metal Oxide Semiconductors (CMOS). Since CMOS has no intermediate voltage levels like those of bipolar cascode logic, the static L1/static L2 latch for these circuits requires a dynamic L1 stage. Referring to Fig. 1, the circuit shown has two latch sections L1 and L2. Transistors T1, T2, T3, T4 form a standard four-device dynamic storage cell. CP1 and CP2 represent stray capacitance associated with nodes N1, N2, and which are actually the storage medium for the dual polarity input signals. The A clock serves to cause transistors T3 and T4 to conduct and store the data input in the cross-coupled storage. Transistors T5, T6, T7, T8 form a static cross-coupled CMOS latch. Transistor T12 is normally conducting, returning the sources of transistors T5 and T8 to ground, and enabling the L2 latch to remain in its st...