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Installing an Instruction-Buffer on a Processor Memory Interface

IP.com Disclosure Number: IPCOM000048000D
Original Publication Date: 1983-Dec-01
Included in the Prior Art Database: 2005-Feb-08
Document File: 2 page(s) / 50K

Publishing Venue

IBM

Related People

Herrman, BD: AUTHOR [+6]

Abstract

A Processor Memory Interface, such as in an IBM Series/1 processor memory interface,has increased performance for instruction fetches by prefetching instructions and storing them in a high speed instruction-buffer. Prefetching of instructions for storage in an Instruction-Buffer (I-Buffer) can be easily accomplished using the fact that instructions are stored sequentially in memory. The first step is to divide the memory into even and odd word banks so two words can be accessed at one time. When the CPU first requests an instruction fetch, a restart occurs.

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Installing an Instruction-Buffer on a Processor Memory Interface

A Processor Memory Interface, such as in an IBM Series/1 processor memory interface,has increased performance for instruction fetches by prefetching instructions and storing them in a high speed instruction-buffer. Prefetching of instructions for storage in an Instruction-Buffer (I-Buffer) can be easily accomplished using the fact that instructions are stored sequentially in memory. The first step is to divide the memory into even and odd word banks so two words can be accessed at one time. When the CPU first requests an instruction fetch, a restart occurs. The restart sequence causes the addressed data to be fetched from one bank and returned, and the other bank is simultaneously accessed with the data placed into its I-Buffer; from now on when the CPU requests an instruction fetch, the data is returned from the high speed I-Buffer of one bank while the opposite I-Buffer is filled with the next sequential word in memory. Very few things affect this sequential flow. One example would be a Branch. When this occurs, another restart is given. The memory interface control and addressing scheme is illustrated in Fig. 1. The memory access cycle is initiated when the signal 'Memory Interface Cycle' is activated. Address bus bit 14 defines an even or odd word access (address bus bit 15 is the byte indicator, and there are no byte instructions). To initiate a sequence of receiving instructions from the I-Buffer the CPU's microcode signals a restart cycle which will load the I-Buffer from one bank. From then on whenever an instruction is fetched, the microcode signals an I-Buffer cycle. The microcode signals a restart cycle whenever the sequential flow of instructions is interrupted. The timing of these two cycles is shown in Figs. 2 and 3. The Memory Interface Addressing is divided into two halves. The high-order bits, 5 and above, directly feed both banks. The low-order address...