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Browse Prior Art Database

Local Storage Link Registers

IP.com Disclosure Number: IPCOM000048002D
Original Publication Date: 1983-Dec-01
Included in the Prior Art Database: 2005-Feb-08
Document File: 2 page(s) / 54K

Publishing Venue

IBM

Related People

Grice, LE: AUTHOR [+3]

Abstract

A feature is described for use in a processor particularly concerned with floating point operations, although it is also useful for level status block instructions. In the processor, the floating point aspect of operations is integrated into the system and is not an add-on capability as has occurred with other processors. In particular, this processor has a local store and various floating point registers added to accommodate the requirements of the floating point operations. This minimizes situations involving utilization of the stack pointer and updating of the stack pointer as found in the IBM Series/l 4955 processor, for example. With the particular arrangement set forth, there is a substantial performance improvement in floating point operations.

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Local Storage Link Registers

A feature is described for use in a processor particularly concerned with floating point operations, although it is also useful for level status block instructions. In the processor, the floating point aspect of operations is integrated into the system and is not an add-on capability as has occurred with other processors. In particular, this processor has a local store and various floating point registers added to accommodate the requirements of the floating point operations. This minimizes situations involving utilization of the stack pointer and updating of the stack pointer as found in the IBM Series/l 4955 processor, for example. With the particular arrangement set forth, there is a substantial performance improvement in floating point operations. The Series/1 4955 processor has a single local storage link register (LSLR) which only increments. Here, the processor has two LSLRs. Fig. 1 shows the two local storage link registers (LSLR) 1 and 2 and the local storage address register (LSAR) 3. Each time the local storage 4 is accessed, the adjacent word address may be placed in either LSLR to allow the next higher or lower word in local storage to be easily accessed. LSLR2 (block
2) decrements instead of increments if the decrement control latch 5 is set. There is also a read-only storage control field decode which inhibits changing the LSLRs for that cycle called "not clock link register" (NCKLR). LSLR1 (block 1) is helpful in writing microcode to step through local storage, e.g., for loading the Level Status Block. The LSLRs also do a wrap at location 15 back to 8, 31 back to 24, etc., to aid in the Load Multiple and Branch and Store Multiple instructions. The local storage locations are as fol...