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Buried Capacitor Node Probing

IP.com Disclosure Number: IPCOM000048011D
Original Publication Date: 1983-Dec-01
Included in the Prior Art Database: 2005-Feb-08
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Cassarino, JM: AUTHOR

Abstract

This article discloses a technique useful in barrier analysis to determine the electrical characterization of single cells. Previously, all such barrier analysis measurements were made by delamination of the entire surface of the chip down to the silicon surface. This was unacceptable because of high surface leakage during testing. The present technique, however, teaches that by leaving the surface passivation in place over the pn junction, the passivation is maintained and leakage components of 10-12 can be identified. The specific process requires that the chip be delayered in the normal manner down to the nitride surface overlying the semiconductor device.

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Buried Capacitor Node Probing

This article discloses a technique useful in barrier analysis to determine the electrical characterization of single cells. Previously, all such barrier analysis measurements were made by delamination of the entire surface of the chip down to the silicon surface. This was unacceptable because of high surface leakage during testing. The present technique, however, teaches that by leaving the surface passivation in place over the pn junction, the passivation is maintained and leakage components of 10-12 can be identified. The specific process requires that the chip be delayered in the normal manner down to the nitride surface overlying the semiconductor device. The unit is coated with a photoresist and exposed and developed so as to create a via of approximately 3 microns in diameter at the exact center of the node of the device of interest. Following development of the photoresist, the unit is placed in the plasma etcher and etched with carbon tetrafluoride (CF4) for 30 seconds such that only the nitride exposed through the via in the photoresist will be removed down to the gate oxide surface. By removing the nitride layer in this manner, a 3-micron diameter via can be maintained down to the silicon surface in the center of the device of interest. The unit may now be acid etched to remove the gate oxide such that the underlying silicon surface can be exposed and ready for probing in the usual manner, because in this technique the nitr...