Browse Prior Art Database

Flush-Through Latch

IP.com Disclosure Number: IPCOM000048032D
Original Publication Date: 1981-Dec-01
Included in the Prior Art Database: 2005-Feb-08
Document File: 2 page(s) / 33K

Publishing Venue

IBM

Related People

Puri, YK: AUTHOR [+2]

Abstract

The above circuit schematic diagram illustrates the flush-through latch. The object of the circuit is to transfer the state A from the input terminal to the output terminal and maintain that state at the output terminal.

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Flush-Through Latch

The above circuit schematic diagram illustrates the flush-through latch. The object of the circuit is to transfer the state A from the input terminal to the output terminal and maintain that state at the output terminal.

The A input is applied to the gates of transistor T1 and transistor T4. Transistor T1 is part of the inverter circuit so that A is output to the gate of transistor T2. Thus when the input A is high, transistor T2 is off and transistor T4 is on. A periodic clock waveform C is up, transistor T5 is on, and since transistor T4 is on, the potential at the node 1 is down. Since node 1 is connected to the gate of transistor T6, transistor T6 is off. Although the clock waveform C will turn transistor T3 on, T2 is off and therefore the potential at node 2 is high, which is the potential applied to the output terminal. The potential at node 2 is also applied to the gate of the transistor T7, holding it on and thereby latching the state of the output 40 of the circuit.

If the input A were down, transistor T1 would not be conducting and therefore transistor T2 would be on and transistor T4 would not be conducting. Thus when the clock is high, transistor T2 and transistor T3 would be conducting. Therefore, node 2 would be low, and the output would be the low state. Transistor T5 would be conducting but since transistor T4 is not conducting, the node 1 is high. This holds transistor T6 on, thereby grounding the output of the circuit and lat...