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Bit Slipping To Achieve Clock Synchronization

IP.com Disclosure Number: IPCOM000048034D
Original Publication Date: 1981-Dec-01
Included in the Prior Art Database: 2005-Feb-08
Document File: 1 page(s) / 11K

Publishing Venue

IBM

Related People

Higgins, PH: AUTHOR [+2]

Abstract

In attempting to synchronize the pulses generated from an oscillator with a reference pulse sequence, it is conventional to add a pulse to the output pulse train to make the effective clock rate faster, when necessary. This can create the problem, however, of causing non-detection of the added bit by subsequent circuitry. This problem is overcome in the present invention by starting out with a faster clock rate and then selectively deleting pulses from the oscillator output for nominal clock rates and selectively not deleting pulses when the output clock rate is to appear faster than nominal.

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Bit Slipping To Achieve Clock Synchronization

In attempting to synchronize the pulses generated from an oscillator with a reference pulse sequence, it is conventional to add a pulse to the output pulse train to make the effective clock rate faster, when necessary. This can create the problem, however, of causing non-detection of the added bit by subsequent circuitry. This problem is overcome in the present invention by starting out with a faster clock rate and then selectively deleting pulses from the oscillator output for nominal clock rates and selectively not deleting pulses when the output clock rate is to appear faster than nominal.

For example, if an oscillator is set to run one bit per timing frame faster than the nominal bit rate, then in order that the bit rate input to the subsequent circuitry will equal the nominal bit rate, the clock synchronization circuits will nominally delete one bit per timing frame. If the clock correction logic, which compares the oscillator is needed, the output of the oscillator can be adjusted by deleting up to an additional bit per timing frame to effectively slow the output clock rate. Alternately, the clock correction logic can intentionally not delete the bit that is normally deleted in each timing frame when a faster effective clock rate is desired. In this manner, the problem of non-detection of an added bit is avoided.

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