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Pageable Control Memory With Time Overlapped Output and Input Operations

IP.com Disclosure Number: IPCOM000048040D
Original Publication Date: 1981-Dec-01
Included in the Prior Art Database: 2005-Feb-08
Document File: 5 page(s) / 45K

Publishing Venue

IBM

Related People

Gregg, TA: AUTHOR [+3]

Abstract

The Control store CS (Fig. 1) operates in a multiprogrammed mode and can perform operations defined by micro-instruction words of one program, which are contained either in its static (non-alterable) section CSS or in one of its two transient (alterable) sections CST-LO or CST-HI, while simultaneously retrieving a page block of 64 microinstruction words associated with another program (from a backing store) and loading that page into the other transient section.

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Pageable Control Memory With Time Overlapped Output and Input Operations

The Control store CS (Fig. 1) operates in a multiprogrammed mode and can perform operations defined by micro-instruction words of one program, which are contained either in its static (non-alterable) section CSS or in one of its two transient (alterable) sections CST-LO or CST-HI, while simultaneously retrieving a page block of 64 microinstruction words associated with another program (from a backing store) and loading that page into the other transient section.

For application to decoding circuits (not shown) and data paths, control words are read out of CS in parallel groups of four words (quadwords). The locations of quadwords to be read out are specified by readout addressing control circuits 10, via addressing lines 11 and 12. CSS contains 512 quadword storage spaces and is addressed by a 9-bit portion of a 16-bit address function MAR which is coupled to CSS through lines 12. Each transient section contains 32 quadword storage locations which are individually addressable for readout access by a 5-bit address function presented via lines 11. Each such address function consists of a 4-bit portion of the 16-bit MAR function and a 1-bit portion of a 2-bit transient area index (TAI) code, which is defined later in this article.

Page retrieval and loading operations are controlled by circuits 16 in response to requests presented at the decode outputs of CS. Circuits 16 operate independently of both circuits 10 and other (non-request) outputs of CS. Prior to beginning any page retrieval operation, circuits 16 select a (one of two) page storage area in one of the transient sections of CS into which the requested page will be written. The requested page is retrieved from backing storage (not shown) via lines 17, in quadword units (i.e., in 16 discrete transfer operations). Each retrieved unit is loaded into a quad-word portion of the preselected area of the preselected transient section via lines 18. At such times, circuits which control readout access to the selected section are degated (blocked), but CSS and the other (unselected) transient section remain potentially accessible for performing other microprogram tasks. The location into which each quadword is written is defined by a 5-bit addressing function communicated from circuits 16 via lines 19.

The (16-bit) address functions issued by circuits 10 represent either "virtual" addresses associated with backing storage, when one or more of the 5 highest order bits are not 0, or "real" addresses in CSS when all 5 highest order bits are are 0. When an address refers to a "real" location in CSS, a quadword is unconditionally read out. However, when an address refers to a "virtual" address currently mapped into a transient section, circuits 10 operate to read a quadword from the appropriate transient section (which is designated by the value of TAI bit zero). The target address of Branch instructions is examined b...