Browse Prior Art Database

Card Operated Attendance Verification Multiplexing Circuitry

IP.com Disclosure Number: IPCOM000048063D
Original Publication Date: 1981-Dec-01
Included in the Prior Art Database: 2005-Feb-08
Document File: 2 page(s) / 39K

Publishing Venue

IBM

Related People

Powell, KE: AUTHOR

Abstract

This circuitry provides for verifying the presence of a cardholder with two access card reading devices over a single pair of electric communication lines. One of the card reading devices is altered for reading in reverse and multiplexing logical circuitry it interposes for permitting but one reading device to operate at a time.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 52% of the total text.

Page 1 of 2

Card Operated Attendance Verification Multiplexing Circuitry

This circuitry provides for verifying the presence of a cardholder with two access card reading devices over a single pair of electric communication lines. One of the card reading devices is altered for reading in reverse and multiplexing logical circuitry it interposes for permitting but one reading device to operate at a time.

The card reading devices are arranged with microswitches at light-emitting diode and detector arrangements for masking out the reading in one direction of card travel. Here, one reading device is arranged for delivering the information in the forward direction and the other in the reverse direction. The central processing unit (CPU) is modified to accept the information in one direction as an indication of the ingress of a card holder, and to accept the same information in the reverse direction as an indication of the egress of that card holder. Acknowledgement and execution signals from the CPU are directed to the proper card reading device by way of the logical circuitry shown in the drawing.

Read data from the card reader 10 is gated through an AND gating circuit 12 and an OR gating circuit 14 to the digital input port of a CPU 16, provided the AND gating circuit 12 is armed. The AND gating circuit 12 is armed when the P terminal of a monostable flip-flop circuit 18 is up to arm an AND gating circuit 20 for bringing the Q terminal another monostable flip-flop circuit 22 up, thus arming the AND gating circuit 12. Similarly, data from the other card reader 30 is gated through an AND...