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Packaging of Silicon Integrated Passive Display

IP.com Disclosure Number: IPCOM000048076D
Original Publication Date: 1981-Dec-01
Included in the Prior Art Database: 2005-Feb-08
Document File: 2 page(s) / 40K

Publishing Venue

IBM

Related People

Warwick, WA: AUTHOR

Abstract

An electrochromic or liquid crystal display includes a silicon wafer on which an array of FETs (field effect transistors) is formed over each of which is deposited a display electrode. The wafer is mounted face down on a sub-carrier which is provided with deposited conductor lines for external connection. Electrical connection between the wafer and the conductors on the sub-carrier is effected by conventional solder reflow techniques. The sub-carrier is provided with an aperture co-extensive with the array to reveal the display electrodes and also to form the side walls of a chamber to contain an electrolyte. The display package is completed with a viewing window to provide a liquid tight modular display.

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Packaging of Silicon Integrated Passive Display

An electrochromic or liquid crystal display includes a silicon wafer on which an array of FETs (field effect transistors) is formed over each of which is deposited a display electrode. The wafer is mounted face down on a sub-carrier which is provided with deposited conductor lines for external connection. Electrical connection between the wafer and the conductors on the sub-carrier is effected by conventional solder reflow techniques. The sub-carrier is provided with an aperture co-extensive with the array to reveal the display electrodes and also to form the side walls of a chamber to contain an electrolyte. The display package is completed with a viewing window to provide a liquid tight modular display.

The display module shown in the drawings comprises a glass frame 10 in which a rectangular hole is formed. The frame 10 is a sub-carrier for a silicon wafer 11 on which an array of display electrodes 12 is formed. Each of these display electrodes may be energized by means of an underlying FET in the silicon. The array of FETs is addressed by means of conductive pads and lines (not visible) along the edges of the wafer.

To provide a conductive path between the pads and external addressing circuitry the wafer is connected by solder reflow connections 13 to surface metallurgy 14 on the surface of the glass frame. These solder connections are encapsulated in an encapsulant 15 which may be solder glass or an organic men...