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Fabrication Procedures for a Self Aligned Depletion Implant Under the Storage Plate of a Double Polysilicon One Device FET Dynamic RAM

IP.com Disclosure Number: IPCOM000048082D
Original Publication Date: 1981-Dec-01
Included in the Prior Art Database: 2005-Feb-08
Document File: 2 page(s) / 13K

Publishing Venue

IBM

Related People

Chao, HH: AUTHOR

Abstract

Three fabrication procedures for making a self aligned depletion implant under a storage plate of a double polysilicon one device FET (field effect transistor) dynamic RAM (random access memory) are described.

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Fabrication Procedures for a Self Aligned Depletion Implant Under the Storage Plate of a Double Polysilicon One Device FET Dynamic RAM

Three fabrication procedures for making a self aligned depletion implant under a storage plate of a double polysilicon one device FET (field effect transistor) dynamic RAM (random access memory) are described.

In order to substantially cut off a subthreshold leakage current, the threshold voltage of a transfer gate of a one device FET dynamic RAM cell can not be scaled down in the same manner as other devices and voltages. However, the signal charge capacity of such a RAM cell will be reduced significantly because this threshold voltage can not be scaled down. Some of this charge capacity loss can be regained by a word line boost technique. However, the full advantage of the word line boost technique can not be obtained unless the threshold voltage of the storage plate is zero or negative.

In the following, three self aligned fabrication procedures aiming to shift the threshold voltage of the storage plate to a negative value are described. With the addition of a few steps, these fabrication procedures are compatible with a conventional double polysilicon gate process.

The first procedure is described as follows:

(1) First gate oxidation.

(2) Blanket enhancement ion implant

(3) Depletion implant mask and depletion ion implant.

(4) First polysilicon deposition and patterning.

(5) First gate oxide etch and second gate oxidation.

(6) Blanket second enhancement ion implant to shift the

(7) Resume the conventional double polysilicon process.

With this procedure, both depletion and enhancement device in the supporting circuits are made using the first poly. The threshold voltage of transfer gate to desired value. on the compensation of the enhancement implants...