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Josephson Soliton Logic and Read-Only Memory Circuits

IP.com Disclosure Number: IPCOM000048089D
Original Publication Date: 1981-Dec-01
Included in the Prior Art Database: 2005-Feb-08
Document File: 3 page(s) / 37K

Publishing Venue

IBM

Related People

Henkels, WH: AUTHOR [+3]

Abstract

Josephson solitons are single flux vortices which exist in Josephson junction transmission lines and which can be propagated along these lines lines by bias currents across the electrodes comprising the transmission lines. The solitons can be written and detected, and can be used to represent information bits. This article describes a family of logic devices using Josephson solitons wherein the solitons are deflected along preferred paths, depending upon the presence of various control signals. Programmed logic arrays (PLAs) are designed to provide a very dense logic family having high margins and low cycle times.

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Josephson Soliton Logic and Read-Only Memory Circuits

Josephson solitons are single flux vortices which exist in Josephson junction transmission lines and which can be propagated along these lines lines by bias currents across the electrodes comprising the transmission lines. The solitons can be written and detected, and can be used to represent information bits. This article describes a family of logic devices using Josephson solitons wherein the solitons are deflected along preferred paths, depending upon the presence of various control signals. Programmed logic arrays (PLAs) are designed to provide a very dense logic family having high margins and low cycle times.

AND Device- The basic logic element is a fork shaped Josephson junction as shown in Fig. 1A. The junction is comprised of a bottom electrode layer M1 and a top electrode layer M2, where a thin insulator (not shown) is located between layers M1 and M2. The thin insulator between M1 and M2 allows Josephson tunneling current to flow between M1 and M2. The active tunnel junction area is indicated by the dashed lines 10. The electrical equivalent circuit of this device is shown in Fig. 1B

A current I(b) is injected across the top electrode between points P and Q. An input soliton at A triggers an output at B, if I(b) is positive. If I(b) is negative, an output is obtained at C. Let I(b) be positive. If a control line 12 (Fig. 2) carries a current I(c) equals -2I(b) over top electrode M2, an output will be triggered at C, not at B. Here, the ground plane M1 is assumed to be the base electrode. For a PLA system, the logic AND array is formed by placing these devices 14 (Fig. 2) in series, as shown in in Fig. 3. A device 14 is personalized when a control line 16 goes over it; otherwise, the line is directed around the device. The control level of metallurgy (third layer) personalizes the device array.

OR/NOR Circuits- A multi-input OR/NOR device is shown in Figs. 4A and 4B. The basic device is the same as that shown in Fig. 2 for the AND circuit. If any or all of the inputs A, B, C are present, an output will be obtained at Y (Fig. 4B).

If none of the inputs are present, an output will be obtained at X. The margins and speeds of this device are the same as that for the AND circuit. For the NOR device of Fig. 4A, the device density is the same as that for the AND circuit, while for the OR device of Fig. 4B, the density is smaller.

Exclusive OR- An exclusive OR circuit can be formed for a combination of AND devices, as shown in Fig. 5. The outputs AB and AB are terminated, while the...