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Two Pass Memory Test

IP.com Disclosure Number: IPCOM000048098D
Original Publication Date: 1981-Dec-01
Included in the Prior Art Database: 2005-Feb-08
Document File: 1 page(s) / 11K

Publishing Venue

IBM

Related People

Yates, LS: AUTHOR

Abstract

Thorough read-only and random access memory contents verification and error detection are provided by utilizing a minimum number of comparison key bytes and two scans of memory.

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Two Pass Memory Test

Thorough read-only and random access memory contents verification and error detection are provided by utilizing a minimum number of comparison key bytes and two scans of memory.

In the first scan of memory, the contents of all 8-bit byte locations are sequentially added to the lowest 8 bits in a 24-bit accumulator. Any overflow from the highest order bit of the accumulator is repeatedly added back to the lowest order bit. Following the first scan, the accumulator contents are compared with a 24-bit expected result. The expected result is comprised of three key bytes made up of 8 bits each. If there is a non-compare, an error is present. If there is a compare, the memory is again scanned.

During the second scan, the contents of all locations are again sequentially added in, the accumulator with a leftward shift of the accumulator for each add operation. The overflow of the highest-order bit is repeatedly added back to the lowest-order bit. Upon completion of the second scan, the accumulator contents are again compared with an expected result comprised of additional three-key bytes. If there is a compare, no errors are considered to exist.

With the above test routine, all odd number bit faults will be detected, and substantially all even number bit faults will be detected.

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