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Multi-Bit Storage FET EAROM Cell

IP.com Disclosure Number: IPCOM000048120D
Original Publication Date: 1981-Dec-01
Included in the Prior Art Database: 2005-Feb-08
Document File: 3 page(s) / 47K

Publishing Venue

IBM

Related People

Alberts, GS: AUTHOR [+2]

Abstract

An electrically alterable read only memory (EAROM) cell of the field-effect transistor (FET) type is provided which is capable of storing a large number of digits of information. The cell includes a structure having a control gate and at least one floating gate with a doped insulator system disposed between the floating gate and the control gate. The floating gate and a portion of the control gate are spaced from the surface of a semiconductor substrate. by a thin insulating layer and are disposed between first and second diffusion regions defining a channel region, with a substantial portion of the floating gate being located over the channel region and the remaining portion of the floating gage being located over one of the first and second diffusion regions.

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Multi-Bit Storage FET EAROM Cell

An electrically alterable read only memory (EAROM) cell of the field-effect transistor (FET) type is provided which is capable of storing a large number of digits of information. The cell includes a structure having a control gate and at least one floating gate with a doped insulator system disposed between the floating gate and the control gate. The floating gate and a portion of the control gate are spaced from the surface of a semiconductor substrate. by a thin insulating layer and are disposed between first and second diffusion regions defining a channel region, with a substantial portion of the floating gate being located over the channel region and the remaining portion of the floating gage being located over one of the first and second diffusion regions. By applying appropriate voltages between the control gate and the one diffusion region, the floating gate may be selectively charged to varying degrees and discharged. The doped insulator system is preferably a graded band gap or silicon rich dioxide structure of the dual electron injector type, as described, e.g., in an article by D.J. DiMaria, et al., entitled "Electrically Alterable Memory Using a Dual Electron Injector Structure," IEEE Electron Device Letters EDL-1, 179-181 (September 1980).

An embodiment of this cell is illustrated in Fig. 1 wherein a first floating gate FGs has a portion thereof disposed over a first N+ diffusion region S and a second floating gate FGd has a portion thereof disposed over a second N+ diffusion region D, and a first doped insulator system DISI is disposed between first floating gate FGs and control gate CG and a second doped insulator system DIS2 is disposed between second floating gate FGd and control gate CG. As is known, by applying an appropriate voltage between region S and control gate CG, having a terminal Vcg, floating threshold Vt over a portion of the channel region adjacent first N+ diffusion region S. In a similar manner, the voltage threshold Vt over a portion of the channel region adjacent second N+ diffusion region D may also be altered. The extend to which the threshold voltage near first region S has been altered May be determined by applying an appropriate voltage to second region D and sensing the current flowing in the channel region between first and second regions S and D. The extend to which the threshold voltage has been altered near second region D may be determined in a similar manner by applying an appropriate voltage to first region S.

The cell basically consists of three devices or transistors Td, Tc and Ts connected as indicated in Fig. 2. Under a bias condition, the cell current Ids has a magnitude that strongly depends on the characteristics of transistors Td, Tc and Ts. By controlling the threshold voltage Vtd of device Td and the threshold voltage Vts of device Ts, in the manner described hereinabove, the cell current Ids As readily controlled.

If the threshold voltage V...