Browse Prior Art Database

Cluster Regeneration and Amplification of Memory Cells

IP.com Disclosure Number: IPCOM000048122D
Original Publication Date: 1981-Dec-01
Included in the Prior Art Database: 2005-Feb-08
Document File: 2 page(s) / 40K

Publishing Venue

IBM

Related People

Pricer, WD: AUTHOR

Abstract

Cluster regeneration and amplification of signals in a one-device cell random-access memory is provided for low power operation without significant semiconductor chip area penalty by connecting a bootstrap circuit to a common point, with the switch or transistor at each of a group of cells being disposed between the common point and an associated storage capacitor. The group or cluster of cells is isolated by a cluster address transistor connected between the cluster and a bit/sense line.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 71% of the total text.

Page 1 of 2

Cluster Regeneration and Amplification of Memory Cells

Cluster regeneration and amplification of signals in a one-device cell random-access memory is provided for low power operation without significant semiconductor chip area penalty by connecting a bootstrap circuit to a common point, with the switch or transistor at each of a group of cells being disposed between the common point and an associated storage capacitor. The group or cluster of cells is isolated by a cluster address transistor connected between the cluster and a bit/sense line.

A memory system is illustrated in Fig. 1 which has a bootstrap circuit 10 connected to a cluster of four one-device cells A, B, C and D at a common point or node N, with node N being isolated from other circuitry, such as the bit/sense line, which may be made of metal, and the sense amplifier and driver circuits, by cluster address transistor 1.

To refresh, e.g., the information stored in cell A, transistors 2 and 3 of bootstrap circuit 10 are turned on to reference the common node N to ground, which may alternatively be referenced to ground through cluster address transistor 1. Then, transistors 2 and 3 are turned off, and transistor 4 is turned on. The transistor of cell A is now turned on, bringing the common none N to a voltage substantially equal to that across the storage capacitor Cs of cell A. Transistor 4 is turned off, and transistor 5 is bootstrapped through bootstrap capacitor Cb by a positive pulse at its drain....