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Miscompare Validation Test System

IP.com Disclosure Number: IPCOM000048129D
Original Publication Date: 1981-Dec-01
Included in the Prior Art Database: 2005-Feb-08
Document File: 4 page(s) / 53K

Publishing Venue

IBM

Related People

Farrell, WR: AUTHOR [+4]

Abstract

A key limitation of using the logic compare test approach, comparing the logic responses from a "golden" (known to be good) card with the responses from the device under test (DUT), is that the tester may detect a logic miscompare between the "golden" card and the DUT, but both cards may be good. There are conditions, e.g., along shift registers, logic memory devices, and latches, when the same stimuli applied to two good cards will create different logic responses due to the internal states of the card. This limitation hinders fault detection and fault diagnosis. This article describes and illustrates a logic compare test technique that overcomes this limitation.

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Miscompare Validation Test System

A key limitation of using the logic compare test approach, comparing the logic responses from a "golden" (known to be good) card with the responses from the device under test (DUT), is that the tester may detect a logic miscompare between the "golden" card and the DUT, but both cards may be good. There are conditions, e.g., along shift registers, logic memory devices, and latches, when the same stimuli applied to two good cards will create different logic responses due to the internal states of the card. This limitation hinders fault detection and fault diagnosis. This article describes and illustrates a logic compare test technique that overcomes this limitation. In the preceding article, there is illustrated a technique that minimizes the different types of fixtures required to test various card types, improves test detection and module failure isolation, and enables open/short testing and logic testing to be done on the same tester. The All Nodes Test System (ANTS) requires more test time to monitor the nets per test pattern as compared to the conventional approach, although ANTS compared better overall. The Miscompare Validation Test System (MVTS) uses the advantages of ANTS and enables a reduction in the time per test pattern compared to the conventional approaches.

Logic simulators use three values to identify the logic response values, i.e., logic "1", logic "0", and logic "X". A logic response "X" indicates that the response may be either logic "1" or logic '0", but the simulator cannot predict which logic value will be on the monitored net. Generally, most "X" responses are at the beginning of the test sequence and fewer "X" responses are near the end of the test sequence. The test stimuli for a printed circuit board (PCB) is created by automatic test generators (ATGs) or manually supplied by the designer. Logic simulators use the stimuli to create the logic responses per PCB f physical net. The simulator output is reduced, by software program, prior to the release of the test data to manufacturing to MDTS Valid Miscompare/Ignore Miscompare (VM/IM) test data. The following criteria are used to reduce the simulator output test data to VM/IM: a) If the simulator predicted known logic'(i.e.. logic "1" or logic "0") response, then VM/NOVM indicates valid miscompare where miscompare refers to a condition when "golden" card logic value does not compare with DUT logic value. b) If the simulator predicts an unknown value or logic "X"

response, then VM/IM indicates an ignore miscompare condition.

It should be noted that the VM/IM test data volume is small as compared to the simulator created test data.

The same stimuli are applied to both the "golden" card and DUT.

The tester's "golden" card responses are compared with DUT responses. The stimuli application is interrupted only if a miscomparison is elected. VM/LM data is used to determine whether to ignore the detected miscomparison. If VN/IM give...