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Microprocessor Assisted Channel Interface Controller for a Multipath Channel to Channel Adapter

IP.com Disclosure Number: IPCOM000048136D
Original Publication Date: 1981-Dec-01
Included in the Prior Art Database: 2005-Feb-08
Document File: 5 page(s) / 78K

Publishing Venue

IBM

Related People

Hopko, RM: AUTHOR [+3]

Abstract

Many I/O devices have embedded within themselves a microprocessor which controls some of their assigned functions. There are difficult decisions to be made in the design of such devices concerning which of the functions should be implemented strictly in hardware and which should be relegated to the microprocessor and its ROS stored programs. When the device is a multi-pathed channel to channel adapter, such as that shown in Fig. 1, these design problems are multiplied by the number of channels which are attached to it. Not only must the device maintain its logical connection to each of the channels, but it must also be capable of dividing its attention efficiently among all of them.

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Microprocessor Assisted Channel Interface Controller for a Multipath Channel to Channel Adapter

Many I/O devices have embedded within themselves a microprocessor which controls some of their assigned functions. There are difficult decisions to be made in the design of such devices concerning which of the functions should be implemented strictly in hardware and which should be relegated to the microprocessor and its ROS stored programs. When the device is a multi-pathed channel to channel adapter, such as that shown in Fig. 1, these design problems are multiplied by the number of channels which are attached to it. Not only must the device maintain its logical connection to each of the channels, but it must also be capable of dividing its attention efficiently among all of them. Described herein is a method to allow control of several interfaces in a multiple channel to channel, distributed processing communications environment.

Almost every interface channel has associated with it a distinct, standardized protocol to which all attached control units or devices must adhere. Thus, there is a detailed definition of the information formats and signal sequences necessary to direct the flow of data between control units and the computer main storage. In this application, each interface controller must recognize and act upon all initial selection, data transfer, and disconnection sequences from its attached channel, while allowing a microprocessor time to complete the task of servicing the other controllers as well.

As shown, the simple functions which require speed and quick response to the channel are implemented in hardware, while those requiring calculations, decisions, or compilations are left to the microcode, taking full advantage of the breaks allowed in channel timing. This method allows efficient communication in strict conformity with block multiplexer channel operations, and can be implemented at minimum hardware cost.

The asynchronous channel tags are synchronized to the microprocessor cycles by a sequential ring of clocks, DO through D5, which are derived from the microprocessor's oscillator. Channel output tags are trapped at the clock intervals shown in the accompanying logic diagrams while the set, reset and other controls emanating from the microprocessor always occur at D2 time, the center of the write cycle.

A single, byte wide interfacing register, hereafter called the IFC register, serves as a buffer between the channel data lines, the common bus of the channel to channel adapter, and I/O busses of the controlling microprocessor. This IFC register, as shown in Fig. 2, may be loaded from the channel data output lines, from the microprocessor, or from the common bus. It may have its contents transferred out to the channel data input lines, to the microprocessor, or to the common bus. The register may at any one time contain address, command, status, sense or character data depending on the source and destination of the...