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Implementation of Main Frame System Using a Microcoded Microprocessor and a Coded Microporcessor

IP.com Disclosure Number: IPCOM000048139D
Original Publication Date: 1981-Dec-01
Included in the Prior Art Database: 2005-Feb-08
Document File: 3 page(s) / 33K

Publishing Venue

IBM

Related People

Agnew, PW: AUTHOR [+6]

Abstract

A microprocessor based implementation of main frame architecture which combines the excellent cost/performance of on chip microcode for the most critical functions with the flexibility, extendability, and low development cost of off-chip microprocessor code for less critical functions is described. State of the art microprocessors achieve excellent cost/ performance by combining on a single chip, the necessary data flow, register array, and controls. Thus, the critical path through these functional elements is very short, both physically and electrically. However, the capacity of the control store is limited by the space available on the microprocessor chip. This, in turn, limits the complexity of the machine architecture that can be implemented entirely on or with one microprocessor.

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Implementation of Main Frame System Using a Microcoded Microprocessor and a Coded Microporcessor

A microprocessor based implementation of main frame architecture which combines the excellent cost/performance of on chip microcode for the most critical functions with the flexibility, extendability, and low development cost of off- chip microprocessor code for less critical functions is described. State of the art microprocessors achieve excellent cost/ performance by combining on a single chip, the necessary data flow, register array, and controls. Thus, the critical path through these functional elements is very short, both physically and electrically. However, the capacity of the control store is limited by the space available on the microprocessor chip. This, in turn, limits the complexity of the machine architecture that can be implemented entirely on or with one microprocessor.

The typical main frame architecture requires roughly four times as much microcode as can be contained in one state of the art microprocessor. Yet, the short critical path means that those instructions that can be implemented by on- chip microcode.

One solution to this problem is to employ one microprocessor containing specialized microcode and one off the shelf microprocessor. The main frame's instructions and registers are them partitioned as follows.

One processor, called the "Primary" processor, contains the general purpose registers (GPRs) and contains the microcode for all functions that make heavy use of GPRs. It performs I-Cycles (fetch, decode, and effective address calculation) for all instructions. It also performs E-Cycles (instruction execution) for the most used instructions, i.e., for almost all instructions except Floating Point instructions, Decimal instructions and Privileged instructions. In a typical instruction mix, the instructions that the Primary processor executes constitute about 95 percent of the instructions by frequency of occurrence and about 50 percent of the instructions by execution time. Because the Primary processor also performs I-Cycles for all instructions, it actually runs more than 50 percent of the time.

The Primary processor is also responsible for detecting instructions for which it does not contain the execution microcode. It hands over control to the other or "Secondar...