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Masking Technique to Fabricate Short Channel MOSFET for Periphery of RAM Chip

IP.com Disclosure Number: IPCOM000048160D
Original Publication Date: 1981-Dec-01
Included in the Prior Art Database: 2005-Feb-08
Document File: 3 page(s) / 39K

Publishing Venue

IBM

Related People

De La Moneda, FH: AUTHOR

Abstract

For the double polysilicon process, channel length L between the source and drain is determined by the following process biases occurring between the definition of the photoresist image and the drive in of the source drain implant, as shown in Fig. 1: Delta L=2x(Polysilicon gate etching (1) minus polysilicon sidewall oxidation (2) plus etching of polysilicon sidewall silicon dioxide(3) plus lateral diffusion (4))

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Masking Technique to Fabricate Short Channel MOSFET for Periphery of RAM Chip

For the double polysilicon process, channel length L between the source and drain is determined by the following process biases occurring between the definition of the photoresist image and the drive in of the source drain implant, as shown in Fig. 1: Delta L=2x(Polysilicon gate etching (1) minus polysilicon

sidewall oxidation (2) plus etching of polysilicon

sidewall silicon dioxide(3) plus lateral

diffusion (4))

This formula simplifies the actual physical situation somewhat.

The position of the edges of the implanted species depends on their projected range and the taper of the etched polysilicon sidewall.

The larger penetration of the sidewall by the implant, the larger Delta L is, as illustrated in Fig. 1.

Increased Delta L has adverse effects on devices of minimum channel length, reducing their threshold and punch-through voltages below specifications. One solution to this problem is to change the dose and energy of the implant. However, a substantial change in dose and/or energy is unsatisfactory since they have been selected to optimize diffusion sheet resistance and device parameters. Another solution is to compensate for the increment in Delta L by increasing gate lengths at the mask level. This may increase chip size and lower yields because of the well-known relationship between yield and active device area.

Still another solution is to anisotropically etch the first polysilicon layer (poly- 1) to produce gates and storage capacitor plates with near vertical sidewalls which can block the implant with high resolution, as illustrated in Fig. 2.

Experimental data from an anisotropically etched product show a decrease in Delta L of 0.7 micron. Unfortunately, the same d...